TA1360ANG Datasheet, PDF (100/108 Pages) Toshiba Semiconductor – TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

TA1360ANG
Note Characteristics
Test Conditions
V01 VP output pulse
width, Vertical
free-run (maximum
pull-in range)
1. Input signal D (shown in the figure below) to TP 16, and signal E (shown in the figure below) to
#24 (FBP input).
2. Measure VP output pulse width (VPw) according to TP 27 output waveform.
3. Measure VP pull-in range (VPt0) according to TP 27 output waveform.
4. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure pull-in range VPt1,
VPt2, VPt3, VPt4, VPt5, and VPt6 as in the step 3 above.
Signal D
(TP 16 input signal)
2.35 µs
29.63 µs
4V
Signal E
(#24 input waveform)
5.6 µs
9V
GND
#24
input waveform
TP 27 waveform
VPw
VPt
V02 Vertical minimum
pull-in range
1. Repeat the step 1 of Note# V01.
2. Input signal F (shown in the figure below) to TP 15.
3. Increase signal-F cycle from 30H. Measure the cycle (T_VPULL) when phase locks with that of
TP 27.
Signal F (TP 15
waveform input)
3H
#24
input waveform
TP 27 waveform
T_VPULL
100
2003-01-21