MSP432P401R Datasheet, PDF (99/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
Table 6-31. SYS_PERIHALT_CTL Register Description (continued)
BIT
FIELD
12
eUB3
TYPE
RW
RESET
0h
DESCRIPTION
0b = IP operation unaffected when CPU is halted
11
eUB2
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
10
eUB1
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
9
eUB0
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
8
eUA3
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
7
eUA2
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
6
eUA1
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
5
eUA0
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
4
T32
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
3
TA3
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
2
TA2
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
1
TA1
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
0
TA0
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
1b = freezes IP operation when CPU is halted
6.9.3 Bootstrap Loader (BSL)
After any POR class reset, the MSP432P401x devices automatically check for presence of user code in
the flash. If the user code is not present, the BSL routine is invoked.
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Detailed Description
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