MSP432P401R Datasheet, PDF (25/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
Table 5-13. LPM3, LPM4 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ORIGINAL
OPERATING MODE
FINAL OPERATING
MODE
TEST CONDITIONS
LATENCY
TYP MAX
t_{AMLDO0_LPMx0} ⁽¹⁾
AM_LDO_VCORE0
LPM3_LPM4_VCORE0
Transition from
AM_LDO_VCORE0 to
LPM3 or LPM4 at
VCORE0.
SELM = 3,
DCO frequency =
16 MHz
SELM = 3,
DCO frequency =
24 MHz
TBD TBD
22
24
t_{LPMx0_AMLDO0_NORIO} ⁽²⁾
LPM3_LPM4_VCORE0
AM_LDO_VCORE0
Transition from LPM3 or
LPM4 at VCORE0 to
AM_LDO_VCORE0
through wake-up event
from nonglitch filter type
I/O.
SELM = 3,
DCO frequency =
16 MHz
SELM = 3,
DCO frequency =
24 MHz
TBD TBD
10
15
t_{LPMx0_AMLDO0_GFLTIO} ⁽²⁾
LPM3_LPM4_VCORE0
AM_LDO_VCORE0
Transition from LPM3 or
LPM4 at VCORE0 to
AM_LDO_VCORE0
through wake-up event
from glitch filter type I/O,
GLTFLT_EN = 1
SELM = 3,
DCO frequency =
16 MHz
SELM = 3,
DCO frequency =
24 MHz
TBD TBD
10
16
t_{AMLDO1_LPMx1} ⁽¹⁾
AM_LDO_VCORE1
LPM3_LPM4_VCORE1
Transition from
AM_LDO_VCORE1 to
LPM3 or LPM4 at
VCORE1.
SELM = 3,
DCO frequency =
32 MHz
TBD TBD
t_{AMLDO1_LPMx1} ⁽¹⁾
AM_LDO_VCORE1
LPM3_LPM4_VCORE1
Transition from
AM_LDO_VCORE1 to
LPM3 or LPM4 at
VCORE1
SELM = 3,
DCO frequency =
48 MHz
21
23
t_{LPMx1_AMLDO1_NORIO} ⁽²⁾
LPM3_LPM4_VCORE1
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1
through wake-up event
from nonglitch filter type
I/O.
SELM = 3,
DCO frequency =
32 MHz
TBD TBD
t_{LPMx1_AMLDO1_NORIO} ⁽²⁾
LPM3_LPM4_VCORE1
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1
through wake-up event
from nonglitch filter type
I/O.
SELM = 3,
DCO frequency =
48 MHz
10
15
t_{LPMx1_AMLDO1_GFLTIO} ⁽²⁾
LPM3_LPM4_VCORE1
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1
through wake-up event
from glitch filter type I/O,
GLTFLT_EN = 1.
SELM = 3,
DCO frequency =
32 MHz
TBD TBD
t_{LPMx1_AMLDO1_GFLTIO} ⁽²⁾
LPM3_LPM4_VCORE1
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1
through wake-up event
from glitch filter type I/O,
GLTFLT_EN = 1
SELM = 3,
DCO frequency =
48 MHz
10
16
(1) This is the latency from WFI instruction execution by CPU to LPM3 or LPM4 entry.
(2) This is the latency from I/O wake-up event to MCLK clock start at device pin.
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
µs
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Specifications
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