MSP432P401R Datasheet, PDF (90/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
PIN NAME
P3.3/PM_UCA2TXD/
PM_UCA2SIMO
P3.4/PM_UCB2STE
P3.5/PM_UCB2CLK
P3.6/PM_UCB2SIMO/
PM_UCB2SDA
P3.7/PM_UCB2SOMI/
PM_UCB2SCL
P7.0/PM_SMCLK/
PM_DMAE0
P7.1/PM_C0OUT/
PM_TA0CLK
P7.2/PM_C1OUT/
PM_TA1CLK
P7.3/PM_TA0.0
P7.4/PM_TA1.4/C0.5 ⁽¹⁾
P7.5/PM_TA1.3/C0.4 ⁽¹⁾
P7.6/PM_TA1.2/C0.3 ⁽¹⁾
P7.7/PM_TA1.1/C0.2 ⁽¹⁾
Table 6-20. Default Mapping (continued)
PxMAPy MNEMONIC
PM_UCA2TXD/
PM_UCA2SIMO
PM_UCB2STE
PM_UCB2CLK
PM_UCB2SIMO/
PM_UCB2SDA
PM_UCB2SOMI/
PM_UCB2SCL
PM_SMCLK/
PM_DMAE0
PM_C0OUT/
PM_TA0CLK
PM_C1OUT/
PM_TA1CLK
PM_TA0.0
PM_TA1.4
PM_TA1.3
PM_TA1.2
PM_TA1.1
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_B2 clock input/output (direction controlled by eUSCI)
eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)/
eUSCI_B2 I²C data (open drain and direction controlled by eUSCI)
eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)/
eUSCI_B2 I²C clock (open drain and direction controlled by eUSCI)
DMAE0 input
SMCLK
Timer_A0 external clock input
Comparator-E0 output
Timer_A1 external clock input
TA0 CCR0 capture input CCI0A
TA1 CCR4 capture input CCI4A
TA1 CCR3 capture input CCI3A
TA1 CCR2 capture input CCI2A
TA1 CCR1 capture input CCI1A
Comparator-E1 output
TA0 CCR0 compare output Out0
TA1 CCR4 compare output Out4
TA1 CCR3 compare output Out3
TA1 CCR2 compare output Out2
TA1 CCR1 compare output Out1
6.8.3 Timer_A
Timers TA0, TA1, TA2 and TA3 are 16-bit timers/counters (Timer_A type) with five capture/compare
registers each. Each timer supports multiple capture/compares, PWM outputs, and interval timing. Each
has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions
and from each of the capture/compare registers.
6.8.3.1 Timer_A Signal Connection Tables
Table 6-21 through Table 6-24 list the interface signals of the Timer_A modules on the device and
connections of the interface signals to the corresponding pins or internal signals. The following rules apply
to the naming conventions used.
• The first column lists the device level pin or internal signal that sources the clocks and/or triggers into
the Timer. The default assumption is that these are pins, unless specifically marked as (internal).
Nomenclature used for internal signals is as follows:
– CxOUT: output from Comparator 'x'.
– TAx_Cy: Output from Timer 'x', Capture/Compare module 'y'.
• The second column lists the input signals of the Timer module.
• The third column lists the submodule of the Timer and also implies the functionality (Timer, Capture
(Inputs or Triggers), or Compare (Outputs or PWM)).
• The fourth column lists the output signals of the Timer module.
• The fifth column lists the device level pin or internal signal that is driven by the outputs of the Timer.
The default assumption is that these are pins, unless specifically marked as (internal).
NOTE
The pin names listed in the tables are the complete names. It is the responsibility of the
software to ensure that the pin is used in the intended mode for the targeted Timer
functionality.
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Detailed Description
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