MSP432P401R Datasheet, PDF (18/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
5.8 Operating Mode Execution Frequency vs Flash Wait-State Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
NUMBER OF
FLASH WAIT
STATES
FLASH READ
MODE
MAXIMUM SUPPORTED MCLK FREQUENCY⁽¹⁾ , ⁽²⁾
AM_LDO_VCORE0,
AM_DCDC_VCORE0
AM_LDO_VCORE1,
AM_DCDC_VCORE1
UNIT
f_{MAX_NRM_FLWAIT0}
0
Normal read
mode
12
16
MHz
f_{MAX_NRM_FLWAIT1}
1
Normal read
mode
24
32
MHz
f_{MAX_NRM_FLWAIT2}
2
Normal read
mode
24
48
MHz
f_{MAX_ORM_FLWAIT0}
0
Other read
modes ⁽³⁾
6
8
MHz
f_{MAX_ORM_FLWAIT1}
1
Other read
modes ⁽³⁾
12
16
MHz
f_{MAX_ORM_FLWAIT2}
2
Other read
modes ⁽³⁾
18
24
MHz
f_{MAX_ORM_FLWAIT3}
3
Other read
modes ⁽³⁾
24
32
MHz
f_{MAX_ORM_FLWAIT4}
4
Other read
modes ⁽³⁾
24
40
MHz
f_{MAX_ORM_FLWAIT5}
5
Other read
modes ⁽³⁾
24
48
MHz
(1) Violation of the maximum frequency limitation for a given wait-state configuration results in nondeterministic data or instruction fetches
from the flash memory.
(2) In low-frequency active modes, the flash can always be accessed in zero wait-state because the maximum MCLK frequency is limited to
128 kHz.
(3) Other read modes refer to Read Margin 0/1, Read Margin 0B/1B, Program Verify, Erase Verify, and Leakage Verify.
18
Specifications
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