MSP432P401R Datasheet, PDF (80/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
Table 6-11. SYS_NMI_CTLSTAT Register Description (continued)
BIT
FIELD
0
CS_SRC
TYPE
RW
RESET
1h
DESCRIPTION
0b = Disables CS interrupt as a source of NMI
1b = Enables CS interrupt as a source of NMI
6.6.2 Device-Level User Interrupts
Table 6-12 lists the various interrupt sources and their connection to the NVIC inputs
NOTE
Some sources may have multiple interrupt conditions, in which case the appropriate interrupt
status/flag register of the source must be examined to differentiate between the generating
conditions.
Table 6-12. NVIC Interrupts
NVIC INTERRUPT INPUT
INTISR[0]
INTISR[1]
INTISR[2]
INTISR[3]
INTISR[4]
INTISR[5]
INTISR[6]
INTISR[7]
INTISR[8]
INTISR[9]
INTISR[10]
INTISR[11]
INTISR[12]
INTISR[13]
INTISR[14]
INTISR[15]
INTISR[16]
INTISR[17]
INTISR[18]
INTISR[19]
INTISR[20]
INTISR[21]
INTISR[22]
INTISR[23]
INTISR[24]
INTISR[25]
INTISR[26]
INTISR[27]
INTISR[28]
INTISR[29]
INTISR[30]
SOURCE
PSS ⁽¹⁾
CS ⁽¹⁾
PCM ⁽¹⁾
WDT_A
FPU_INT ⁽²⁾
Flash Controller
COMP_E0
COMP_E1
Timer_A0
Timer_A0
Timer_A1
Timer_A1
Timer_A2
Timer_A2
Timer_A3
Timer_A3
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
eUSCI_B0
eUSCI_B1
eUSCI_B2
eUSCI_B3
ADC14
Timer32_INT1
Timer32_INT2
Timer32_INTC
AES256
RTC_C
DMA_ERR
FLAGS IN SOURCE
Combined interrupt from flags in the FPSCR (part of Cortex-M4 FPU)
Flash Controller interrupt flags
Comparator_E0 interrupt flags
Comparator_E1 interrupt flags
TA0CCTL0.CCIFG
TA0CCTLx.CCIFG (x = 1 through 4), TA0CTL.TAIFG
TA1CCTL0.CCIFG
TA1CCTLx.CCIFG (x = 1 through 4), TA1CTL.TAIFG
TA2CCTL0.CCIFG
TA2CCTLx.CCIFG (x = 1 through 4), TA2CTL.TAIFG
TA3CCTL0.CCIFG
TA3CCTLx.CCIFG (x = 1 through 4), TA3CTL.TAIFG
UART/SPI mode Tx/Rx/Status Flags
UART/SPI mode Tx/Rx/Status Flags
UART/SPI mode Tx/Rx/Status Flags
UART/SPI mode Tx/Rx/Status Flags
SPI/I²C mode Tx/Rx/Status Flags (I²C in multi-slave mode)
SPI/I²C mode Tx/Rx/Status Flags (I²C in multi-slave mode)
SPI/I²C mode Tx/Rx/Status Flags (I²C in multi-slave mode)
SPI/I²C mode Tx/Rx/Status Flags (I²C in multi-slave mode)
IFG[0-31], LO/IN/HI-IFG, RDYIFG, OVIFG, TOVIFG
Timer32 Interrupt for Timer1
Timer32 Interrupt for Timer2
Timer32 Combined Interrupt
AESRDYIFG
OFIFG, RDYIFG, TEVIFG, AIFG, RT0PSIFG, RT1PSIFG
DMA error interrupt
(1) This source can also be mapped to the system NMI. Refer to the MSP432P4xx Family Technical Reference Manual for more details.
(2) The FPU of the Cortex-M4 can generate interrupts due to multiple floating point exceptions. It is the responsibility of software to process
and clear the interrupt flags in the FPSCR.
80
Detailed Description
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M