MSP432P401R Datasheet, PDF (98/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
6.8.13 True Random Seed
The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to
implement a deterministic random number generator.
6.9 Code Development and Debug
The MSP432P401x devices support various methods through which the user can carry out code
development and debug on the device.
6.9.1 JTAG and Serial Wire Debug (SWD) Based Development, Debug and Trace
The device supports both 4-pin JTAG and the 2-pin SWD modes of operation. The device is compatible
with all standard Cortex-M4 debuggers available in the market today. The debug logic in the device has
been designed to remain minimally intrusive to the application state. In low-power modes, the user can
enable the debugger to override the state of the PSS, thereby gaining access to debug and trace features.
In 2-pin SWD mode, the TDO pin can be used to export serial wire trace output (SWO) data. In addition,
the TDI and TDO pins of the device can be reassigned as user I/Os. Refer to sections Section 6.10.22
and Section 6.10.23 for more details.
NOTE
If the device has activated debug security, debugger accesses into the device is completely
disabled. The debugger, however, is still be able to scan the run/halt state of the CPU.
Further control of and visibility into the device is possible only after initiating a mass erase of
the device flash contents.
6.9.2 Peripheral Halt Control Register [Address = E004_300Ch]
This register allows the user independent control over the functionality of device peripherals during code
development and debug. When the CPU is halted, the bits in this register can control whether the
corresponding peripheral freezes its operation (such as incrementing, transmit, and receive) or continues
its operation (debug remains nonintrusive). The registers of the peripheral remain accessible irrespective
of the values in the Halt Control Register
Figure 6-16. SYS_PERIHALT_CTL Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMA WDTA ADC1 eUB3 eUB2 eUB1 eUB0 eUA3 eUA2 eUA1 eUA0 T32 TA3 TA2 TA1 TA0
4
rw-0 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
BIT
31-16
15
FIELD
Reserved
DMA
14
WDTA
13
ADC14
Table 6-31. SYS_PERIHALT_CTL Register Description
TYPE
R
RW
RESET
0h
0h
DESCRIPTION
Reserved. Reads return 0h
0b = IP operation unaffected when CPU is halted
RW
1h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
RW
0h
1b = freezes IP operation when CPU is halted
0b = IP operation unaffected when CPU is halted
1b = freezes IP operation when CPU is halted
98
Detailed Description
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