MSP432P401R Datasheet, PDF (23/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
5.10 Timing and Switching Characteristics
5.10.1 Mode Transition Timing
Table 5-11. Active Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ORIGINAL
FINAL OPERATING
OPERATING MODE
MODE
TEST CONDITIONS
LATENCY
TYP MAX
t_{OFF_AMLDO0,100 nF}
t_{OFF_AMLDO0,4.7 µF}
t_{AMLDO0_AMLDO1}
Power Off
AM_LDO_VCORE0
From V_CC reaching 1.65 V to start of
application code. C_VCORE = 100 nF.
4.5
5.2
Power Off
AM_LDO_VCORE0
From V_CC reaching 1.65 V to start of
application code. C_VCORE = 4.7 µF.
4.7
5.8
AM_LDO_VCORE0
Transition from AM_LDO_VCORE0
AM_LDO_VCORE1 to AM_LDO_VCORE1. MCLK
frequency = 24 MHz.
285
340
t_{AMLDO1_AMLDO0}
AM_LDO_VCORE1
Transition from AM_LDO_VCORE1
AM_LDO_VCORE0 to AM_LDO_VCORE0. MCLK
frequency = 24 MHz.
4
5
t_{AMLDO0_AMDCDC0}
AM_LDO_VCORE0
Transition from AM_LDO_VCORE0
AM_DCDC_VCORE0 to AM_DCDC_VCORE0. MCLK
frequency = 24 MHz
15
32
t_{AMDCDC0_AMLDO0}
AM_DCDC_VCORE0
AM_LDO_VCORE0
Transition from
AM_DCDC_VCORE0 to
AM_LDO_VCORE0. MCLK
frequency = 24 MHz
15
27
t_{AMLDO1_AMDCDC1}
AM_LDO_VCORE1
Transition from AM_LDO_VCORE1
AM_DCDC_VCORE1 to AM_DCDC_VCORE1. MCLK
frequency = 48 MHz
15
32
t_{AMDCDC1_AMLDO1}
AM_DCDC_VCORE1
AM_LDO_VCORE1
Transition from
AM_DCDC_VCORE1 to
AM_LDO_VCORE1. MCLK
frequency = 48 MHz
15
27
t_{AMLDO0_AMLF0}
AM_LDO_VCORE0
AM_LF_VCORE0
Transition from AM_LDO_VCORE0
to AM_LF_VCORE0. All high
frequency clock sources (DCO,
HFXT, MODOSC) disabled. SELM =
2, REFO frequency = 128 kHz
115
125
t_{AMLF0_AMLDO0}
AM_LF_VCORE0
AM_LDO_VCORE0
Transition from AM_LF_VCORE0 to
AM_LDO_VCORE0. All high
frequency clock sources (DCO,
HFXT, MODOSC) disabled. SELM =
2, REFO frequency = 128 kHz.
115
130
t_{AMLDO1_AMLF1}
AM_LDO_VCORE1
AM_LF_VCORE1
Transition from AM_LDO_VCORE1
to AM_LF_VCORE1. All high
frequency clock sources (DCO,
HFXT, MODOSC) disabled. SELM =
2, REFO frequency = 128 kHz.
110
115
t_{AMLF1_AMLDO1}
AM_LF_VCORE1
AM_LDO_VCORE1
Transition from AM_LF_VCORE1 to
AM_LDO_VCORE1. All high
frequency clock sources (DCO,
HFXT, MODOSC) disabled. SELM =
2, REFO frequency = 128 kHz.
110
120
UNIT
ms
ms
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
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Specifications
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