MSP432P401R Datasheet, PDF (24/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
Table 5-12. LPM0 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ORIGINAL OPERATING FINAL OPERATING
MODE
MODE
TEST CONDITIONS
LATENCY
TYP
MAX
Transition from
t_{AMLDO0_LPM0LDO0} ⁽¹⁾
AM_LDO_VCORE0
LPM0_LDO_VCORE0 AM_LDO_VCORE0 to
1
LPM0_LDO_VCORE0
Transition from
t_{LPM0LDO0_AMLDO0} ⁽²⁾
LPM0_LDO_VCORE0
AM_LDO_VCORE0
LPM0_LDO_VCORE0 to
AM_LDO_VCORE0
3
4
through I/O interrupt
Transition from
t_{AMDCDC0_LPM0DCDC0} ⁽¹⁾
AM_DCDC_VCORE0 LPM0_DCDC_VCORE0 AM_DCDC_VCORE0 to
1
LPM0_DCDC_VCORE0
t_{LPM0DCDC0_AMDCDC0} ⁽²⁾
LPM0_DCDC_VCORE0
AM_DCDC_VCORE0
Transition from
LPM0_DCDC_VCORE0
to AM_DCDC_VCORE0
through I/O interrupt
3
4
t_{AMLF0_LPM0LF0} ⁽¹⁾
Transition from
AM_LF_VCORE0 to
AM_LF_VCORE0
LPM0_LF_VCORE0
LPM0_LF_VCORE0, All
high frequency clock
1
sources (DCO, HFXT,
MODOSC) disabled
t_{LPM0LF0_AMLF0} ⁽²⁾
LPM0_LF_VCORE0
AM_LF_VCORE0
Transition from
LPM0_LF_VCORE0 to
AM_LF_VCORE0
through I/O interrupt, All
high frequency clock
sources (DCO, HFXT,
MODOSC) disabled
3
4
Transition from
t_{AMLDO1_LPM0LDO1} ⁽¹⁾
AM_LDO_VCORE1
LPM0_LDO_VCORE1 AM_LDO_VCORE1 to
1
LPM0_LDO_VCORE1
Transition from
t_{LPM0LDO1_AMLDO1} ⁽²⁾
LPM0_LDO_VCORE1
AM_LDO_VCORE1
LPM0_LDO_VCORE1 to
AM_LDO_VCORE1
3
4
through I/O interrupt
Transition from
t_{AMDCDC1_LPM0DCDC1} ⁽¹⁾
AM_DCDC_VCORE1 LPM0_DCDC_VCORE1 AM_DCDC_VCORE1 to
1
LPM0_DCDC_VCORE1
t_{LPM0DCDC1_AMDCDC1} ⁽²⁾
LPM0_DCDC_VCORE1
AM_DCDC_VCORE1
Transition from
LPM0_DCDC_VCORE1
to AM_DCDC_VCORE1
through I/O interrupt
3
4
t_{AMLF1_LPM0LF1} ⁽¹⁾
Transition from
AM_LF_VCORE1 to
AM_LF_VCORE1
LPM0_LF_VCORE1
LPM0_LF_VCORE1. All
high frequency clock
1
sources (DCO, HFXT,
MODOSC) disabled
t_{LPM0LF1_AMLF1} ⁽²⁾
LPM0_LF_VCORE1
AM_LF_VCORE1
Transition from
LPM0_LF_VCORE1 to
AM_LF_VCORE1
through I/O interrupt. All
high frequency clock
sources (DCO, HFXT,
MODOSC) disabled
3
4
(1) This is the latency between execution of WFI instruction by CPU to assertion of SLEEPING signal at CPU output.
(2) This is the latency between I/O interrupt event to deassertion of SLEEPING signal at CPU output.
UNIT
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
MCLK
cycles
24
Specifications
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