MSP432P401R Datasheet, PDF (61/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
NOTE
For detailed specifications and information on the programmers model for the Cortex-M4
CPU as well as the associated peripherals mentioned throughout Section 6.1, see the
appropriate reference manual at www.arm.com.
6.2 Memory Map
The device supports a 4-GB address space that is divided into eight 512-MB zones (see Figure 6-1).
0xFFFF_FFFF
0xE000_0000
0xDFFF_FFFF
0xC000_0000
0xBFFF_FFFF
0xA000_0000
0x9FFF_FFFF
0x8000_0000
0x7FFF_FFFF
0x6000_0000
0x5FFF_FFFF
0x4000_0000
0x3FFF_FFFF
0x2000_0000
0x1FFF_FFFF
0x0000_0000
Debug/Trace
Peripherals
Unused
Unused
Unused
Unused
Peripherals
SRAM
Code
Figure 6-1. Device Memory Zones
6.2.1 CODE Zone Memory Map
The region from 0x0000_0000 to 0x1FFF_FFFF is defined as the Code zone, and is accessible through
the ICODE and DCODE buses of the Cortex-M4 processor as well as through the system DMA. This
region maps the flash, the ROM as well as the internal SRAM (permitting optimal single cycle execution
from the SRAM).
The MSP432P401x specific memory map of the Code Zone, as visible to the user code (see Figure 6-2).
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Detailed Description
61