MSP432P401R Datasheet, PDF (16/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
5.4 Recommended External Components^{(1) (2) (3)}
C_DVCC
Capacitor on DVCC pin
For DC-DC operation⁽⁴⁾
For LDO-only operation
MIN
TYP
MAX UNIT
3.3
4.7
µF
3.3
4.7
C_VCORE
Capacitor on VCORE pin
For DC-DC operation, including
capacitor tolerance
For LDO-only operation, including
capacitor tolerance
1.54
4.7
9
µF
70
100
9000
nF
C_AVCC
L_VSW
R_LVSW-DCR
I_SAT-LVSW
Capacitor on AVCC pin
Inductor between VSW and VCORE pins for DC-DC
Allowed DCR for L_VSW
L_VSW saturation current
3.3
4.7
µF
3.3
4.7
13 µH
150
350 mΩ
700
mA
(1) For optimum performance, select the component value to match the typical value given in the table.
(2) Refer to the section on board guidelines for further details on component selection, placement as well as related PCB design guidelines.
(3) Tolerance of the capacitance/inductance values should be taken into account when choosing a component, in order to ensure that the
Min/Max ranges are never exceeded
(4) C_DVCC should not be smaller than C_VCORE
5.5 Operating Mode V_CC Ranges
over operating free-air temperature (unless otherwise noted)
PARAMETER
V_{CC_LDO_VCORE0}
V_{CC_LDO_VCORE1}
V_{CC_DCDC_VCORE0}
V_{CC_DCDC_VCORE1}
V_{CC_VCORE_OFF}
OPERATING MODE
AM_LDO_VCORE0 ^{(1) (2)}
AM_LF_VCORE0
LPM0_LDO_VCORE0
LPM0_LF_VCORE0
LPM3_VCORE0
LPM4_VCORE0
LPM3.5
AM_LDO_VCORE1 ^{(1) (2)}
AM_LF_VCORE1
LPM0_LDO_VCORE1
LPM0_LF_VCORE1
LPM3_VCORE1
LPM4_VCORE1
AM_DCDC_VCORE0 ^{(3) (4)}
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1 ^{(3) (4)}
LPM0_DCDC_VCORE1
LPM4.5 ⁽⁵⁾
TEST CONDITIONS
LDO active, SVSMH enabled, Flash not
active
LDO active, SVSMH enabled, Flash active
LDO active, SVSMH disabled, Flash active
LDO active, SVSMH enabled, Flash active
LDO active, SVSMH disabled, Flash active
MIN MAX UNIT
1.62
3.7
1.71
3.7 _V
1.62
3.7
1.71
3.7
V
1.62
3.7
DC-DC active, SVSMH enabled or disabled
DC-DC active, SVSMH enabled or disabled
LDO disabled, SVSMH enabled or disabled
2.18
3.7 V
2.18
3.7 V
1.62
3.7 V
(1) LPM0 mode associated with each active mode will have a similar V_CC range restriction.
(2) Flash remains active only in active modes and LPM0 modes.
(3) Low frequency active, Low frequency LPM0, LPM3, LPM4, and LPM3.5 modes are based on LDO only.
(4) When V_CC falls below the specified Min value, the DC-DC operation will switch to LDO automatically, as long as the V_CC drop is slower
than the rate that is reliably detected. Refer to <ref> for more details.
(5) Core voltage is switched off in LPM4.5 mode.
16
Specifications
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