MSP432P401R Datasheet, PDF (26/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
Table 5-14. LPM3.5, LPM4.5 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ORIGINAL OPERATING
MODE
FINAL OPERATING
MODE
TEST CONDITIONS
LATENCY
TYP MAX
t_{AMLDO0_LPM3.5} ⁽¹⁾
AM_LDO_VCORE0
LPM3.5
Transition from AM_LDO_VCORE0 to
LPM3.5
22
25
t_{AMDCDC0_LPM3.5} ⁽¹⁾
AM_DCDC_VCORE0
LPM3.5
Transition from AM_DCDC_VCORE0 to
LPM3.5
34
47
t_{AMLF0_LPM3.5} ⁽¹⁾
AM_LF_VCORE0
LPM3.5
Transition from AM_LF_VCORE0 to
LPM3.5
225
240
t_{AMLDO1_LPM3.5} ⁽¹⁾
AM_LDO_VCORE1
LPM3.5
Transition from AM_LDO_VCORE1 to
LPM3.5
22
25
t_{AMDCDC1_LPM3.5} ⁽¹⁾
AM_DCDC_VCORE1
LPM3.5
Transition from AM_DCDC_VCORE1 to
LPM3.5
32
45
t_{AMLF1_LPM3.5} ⁽¹⁾
AM_LF_VCORE1
LPM3.5
Transition from AM_LF_VCORE1 to
LPM3.5
225
240
t_{AMLDO0_LPM4.5} ⁽²⁾
AM_LDO_VCORE0
LPM4.5
Transition from AM_LDO_VCORE0 to
LPM4.5
22
25
t_{AMDCDC0_LPM4.5} ⁽²⁾
AM_DCDC_VCORE0
LPM4.5
Transition from AM_DCDC_VCORE0 to
LPM4.5
32
45
t_{AMLF0_LPM4.5} ⁽²⁾
AM_LF_VCORE0
LPM4.5
Transition from AM_LF_VCORE0 to
LPM4.5
180
195
t_{AMLDO1_LPM4.5} ⁽²⁾
AM_LDO_VCORE1
LPM4.5
Transition from AM_LDO_VCORE1 to
LPM4.5
22
25
t_{AMDCDC1_LPM4.5} ⁽²⁾
AM_DCDC_VCORE1
LPM4.5
Transition from AM_DCDC_VCORE1 to
LPM4.5
22
25
t_{AMLF1_LPM4.5} ⁽²⁾
AM_LF_VCORE1
LPM4.5
Transition from AM_LF_VCORE1 to
LPM4.5
180
195
t_{LPM3.5_AMLDO0} ⁽³⁾
LPM3.5
AM_LDO_VCORE0
Transition from LPM3.5 to
AM_LDO_VCORE0
0.9 0.95
t_{LPM4.5_AMLDO0_SVSMON,100 nF} ⁽³⁾
t_{LPM4.5_AMLDO0_SVSMON,4.7 µF} ⁽³⁾
t_{LPM4.5_AMLDO0_SVSMOFF,100 nF}
(3)
t_{LPM4.5_AMLDO0_SVSMOFF,4.7 µF} ⁽³⁾
LPM4.5
LPM4.5
LPM4.5
LPM4.5
AM_LDO_VCORE0
AM_LDO_VCORE0
AM_LDO_VCORE0
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH enabled while in LPM4.5,
C_VCORE = 100 nF
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH enabled while in LPM4.5,
C_VCORE = 4.7 µF
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH disabled while in LPM4.5,
C_VCORE = 100 nF
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH disabled while in LPM4.5,
C_VCORE = 4.7 µF
1 TBD
TBD TBD
1.7 TBD
TBD TBD
(1) This is the latency from WFI instruction execution by CPU to LPM3.5 mode entry.
(2) This is the latency from WFI instruction execution by CPU to LPM4.5 mode entry.
(3) This is the latency from I/O wake-up event to start of application code.
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ms
ms
ms
26
Specifications
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M