MSP432P401R Datasheet, PDF (69/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
NOTE
Depending on the CPU (MCLK) frequency and the active mode in use, the flash may need to
be accessed with single/multiple wait states. Whenever there is a change required in the
operating frequency, it is the responsibility of the application to ensure that the flash access
wait states are configured correctly before the frequency change is effected. Refer to
electrical specification for details on flash wait state requirements.
6.3.2 SRAM
The MSP432P401x devices support up to 64KB of SRAM memory, with the rest of the 1MB SRAM
memory region treated as reserved. The SRAM memory is aliased in both Code as well as SRAM memory
zones. This enables fast, single cycle execution of code from the SRAM, as the Cortex-M4 processor
pipelines instruction fetches to memory zones other than the Code space. As with the flash memory, the
SRAM can be powered down or placed in a low leakage retention state in low-power modes of operation.
The memory map of SRAM on MSP432P401x devices is shown in Figure 6-7.
Figure 6-7. SRAM Memory Map
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Detailed Description
69