MSP432P401R Datasheet, PDF (72/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
Table 6-6. SYS_SRAM_BANKEN Register Description (continued)
BIT
FIELD
7
BNK7_EN ⁽²⁾
TYPE
RW
RESET
1h
DESCRIPTION
0b = Disables Bank7 of the SRAM
1b = enables Bank7 of the SRAM
6
BNK6_EN ⁽²⁾
RW
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
0b = Disables Bank6 of the SRAM
1b = enables Bank6 of the SRAM
5
BNK5_EN ⁽²⁾
RW
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
0b = Disables Bank5 of the SRAM
1b = enables Bank5 of the SRAM
4
BNK4_EN ⁽²⁾
RW
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
0b = Disables Bank4 of the SRAM
1b = enables Bank4 of the SRAM
3
BNK3_EN ⁽²⁾
RW
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
0b = Disables Bank3 of the SRAM
1b = enables Bank3 of the SRAM
2
BNK2_EN ⁽²⁾
RW
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
0b = Disables Bank2 of the SRAM
1b = enables Bank2 of the SRAM
1
BNK1_EN ⁽²⁾
RW
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
0b = Disables Bank1 of the SRAM
1b = enables Bank1 of the SRAM
0
BNK0_EN
R
1h
When set to 1, bank enable bits for all banks below this bank are set to 1 as
well.
When 1, enables Bank0 of the SRAM
(2) Writes to this bit are allowed ONLY when the SRAM_RDY bit is set to 1. If the bit is 0, it indicates that the SRAM banks are not ready,
and writes to this bit will be ignored
The SRAM Bank Enable Register controls which banks of the SRAM are enabled for read/write accesses.
There is one bit for each available bank (unused bits are reserved). Banks that are not enabled are
powered down to minimize power consumption. Each bit in this register corresponds to one bank of the
SRAM. Banks may only be enabled in a contiguous form. For example:
• If there are eight banks in the device, values of 00111111 and 00000111 are acceptable.
• Values like 00010111 are not valid, and the resultant bank configuration will be set to 00011111.
• For exmaple, for a 4-bank SRAM, the only allowed values are 0001, 0011, 0111, and 1111
72
Detailed Description
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