MSP432P401R Datasheet, PDF (60/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
6 Detailed Description
6.1 Processor and Execution Features
The ARM Cortex-M4 processor provides a high-performance low-cost platform that meets system
requirements of minimal memory implementation, reduced pin count, and low power consumption, while
delivering outstanding computational performance and exceptional system response to interrupts. The
Thumb-2 mixed 16- and 32-bit instruction set of the processor delivers the high performance that is
expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices
(typically in the range of a few kilobytes of memory needed for microcontroller-class applications).
In the MSP432P401x devices, the Cortex-M4 processor can run up to 48 MHz, delivering high
performance for the targeted class of applications, while at the same time maintaining ultra-low active
power consumption.
6.1.1 Floating Point Unit
The Cortex-M4 processor on the MSP432P401x devices includes a tightly coupled Floating Point Unit
(FPU). The FPU is an IEEE754 compliant single precision floating point module supporting add, subtract,
multiply, divide, accumulate, and square-root operations. It also provides conversion between fixed-point
and floating-point data formats and floating point constant instructions.
6.1.2 Memory Protection Unit
The Cortex-M4 processor on the MSP432P401x devices includes a tightly coupled Memory Protection
Unit (MPU) that supports up to eight protection regions. Applications can use this to enforce memory
privilege rules, thus allowing isolation of processes from each other, or enforce memory access rules.
These features are typically required for operating system handling purposes.
6.1.3 Nested Vectored Interrupt Controller
The MSP432P401x devices include a Nested Vectored Interrupt Controller (NVIC) that supports up to 64
interrupts with eight levels of interrupt priority. The Cortex-M4 NVIC architecture allows for low latency,
efficient interrupt/event handling, and seamless integration to device-level power-control strategies.
6.1.4 SYSTICK
The Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-
write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways, and is typically deployed either for Operating System related purposes or as a
general purpose alarm mechanism.
6.1.5 Debug and Trace Features
The Cortex-M4 processor implements a complete hardware debug solution, providing high system visibility
of the processor and memory through either a traditional 4-pin JTAG port or a 2-pin Serial Wire Debug
(SWD) port, typically ideal for microcontrollers and other small package devices. The SWJ-DP interface
combines the SWD and JTAG debug ports into one module, allowing a seamless switch between the 2-
pin and 4-pin modes of operation, depending on application needs.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a
Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through a single pin.
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Detailed Description
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