MSP432P401R Datasheet, PDF (75/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
6.3.3 ROM
The MSP432P401x devices support 32KB of ROM memory, with the rest of the 1-MB region treated as
reserved (for future upgrades). The lower 1KB of the ROM is reserved for TI internal purposes and
accesses to this space will return an error response. The rest of the ROM is used for driver libraries.
NOTE
The entire ROM region returns an error response for write accesses. The lower 1KB of the
ROM always returns an error response for any access.
6.4 DMA
The MSP432P401x devices implement an 8-channel ARM uDMA. This allows eight simultaneously active
channels for data transfer between memory and peripherals without needing to use the bandwidth of the
CPU (thereby reducing power by idling the CPU when there is no data processing required). In addition,
the DMA remains active in multiple low-power modes of operation, allowing for a very low power state in
which data can be transferred at low rates.
For maximum flexibility, up to eight DMA event sources can map to any of the eight channels. This is
controlled through configuration registers in the DMA. In addition, the DMA can generate up to four
interrupt requests (described in Section 6.4.2). For details regarding configuration of the DMA, refer to the
DMA chapter in the MSP432P4xx Family Technical Reference Manual.
Figure 6-11 shows the block diagram of the DMA.
Figure 6-11. DMA Block Diagram
6.4.1 DMA Source Mapping
Each channel of the eight available channels has a control register that can select any of the device level
DMA sources as the final source for that corresponding channel. Table 6-8 lists the sources available for
mapping to each channel, based on the value of the Source Config Register (SRCCFG).
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Detailed Description
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