MSP432P401R Datasheet, PDF (54/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
Table 5-49. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note ⁽¹⁾)
PARAMETER
t_STE,LEAD STE lead time, STE active to clock
TEST CONDITIONS
V_CORE
1.2 V
1.4 V
V_CC
1.62 V
3.7 V
MIN TYP MAX UNIT
65
ns
45
t_STE,LAG STE lag time, Last clock to STE inactive
1.2 V
1.62 V
5
ns
1.4 V
3.7 V
5
t_STE,ACC
STE access time, STE active to SOMI data
out
1.2 V
1.4 V
1.62 V
3.7 V
90
ns
50
t_STE,DIS
STE disable time, STE inactive to SOMI
high impedance
1.2 V
1.4 V
1.62 V
3.7 V
30
ns
10
t_SU,SI
SIMO input data setup time
1.2 V
1.62 V
8
ns
1.4 V
3.7 V
4
t_HD,SI
SIMO input data hold time
1.2 V
1.62 V
7
ns
1.4 V
3.7 V
6
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
1.2 V
1.4 V
1.62 V
3.7 V
50
ns
10
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
1.2 V
1.62 V
0
ns
1.4 V
3.7 V
0
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-5 and Figure 5-6.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-5 and Figure 5-6.
UCMODEx = 01
STE
UCMODEx = 10
CKPL = 0
UCLK
CKPL = 1
t_STE,LEAD
1/f_UCxCLK
t_STE,LAG
SIMO
t_LOW/HIGH
t_LOW/HIGH
t_SU,SI
t_HD,SI
SOMI
t_STE,ACC
t_HD,SO
t_VALID,SO
t_STE,DIS
Figure 5-5. SPI Slave Mode, CKPH = 0
54
Specifications
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