MSP432P401R Datasheet, PDF (9/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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Figure 4-3 shows the pinout of the 64-pin RGC package.
MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
P1.0/UCA0STE
P1.1/UCA0CLK
P1.2/UCA0RXD/UCA0SOMI
P1.3/UCA0TXD/UCA0SIMO
P1.4/UCB0STE
P1.5/UCB0CLK
P1.6/UCB0SIMO/UCB0SDA
P1.7/UCB0SOMI/UCB0SCL
VCORE
DVCC1
VSW
DVSS1
P2.0/PM_UCA1STE
P2.1/PM_UCA1CLK
P2.2/PM_UCA1RXD/PM_UCA1SOMI
P2.3/PM_UCA1TXD/PM_UCA1SIMO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DVCC2
DVSS2
P5.7/TA2.2/VREF-/VeREF-/C1.6
P5.6/TA2.1/VREF+/VeREF+/C1.7
P5.5/A0
P5.4/A1
P5.3/A2
P5.2/A3
P5.1/A4
P5.0/A5
P4.7/A6
P4.6/A7
P4.5/A8
P4.4/HSMCLK/SVMHOUT/A9
P4.3/MCLK/RTCCLK/A10
P4.2/ACLK/TA2CLK/A11
Notes:
1. The secondary digital functions on Ports P2, P3, and P7 are fully mappable. The pin designation shows only the
default mapping. See Table 6-19 for details.
2. Glitch filter is implemented on the following 8 digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
TI recommends connecting the thermal pad on the QFN package to DVSS.
4. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
5. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
6. I²C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-3. 64-Pin RGC Package (Top View)
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Terminal Configuration and Functions
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