MSP432P401R Datasheet, PDF (77/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
NOTE
The PPB space is dedicated only to the Cortex-M4 Private Peripheral Bus.
6.5.1 Master and Slave Access Priority Settings
Table 6-9 lists all the available masters (rows) and their access permissions to slaves (columns). If
multiple masters can access one slave, the table lists access priorities if arbitration is required. A lower
number in the table indicates a higher arbitration priority (the priority is always fixed).
Table 6-9. Master and Slave Access Priority
FLASH MEMORY
ROM
SRAM
PERIPHERALS
ICODE
3
2
DCODE
2 ⁽¹⁾
1
4
NA
2
NA
SBUS
NA
NA
3
2
DMA
1 ⁽²⁾
NA
1 ⁽³⁾
1
(1) Access from the DCODE to flash memory may be restricted if the device is operating in a secure
mode
(2) Access from DMA to flash memory will be restricted to Bank 1 if the device is operating in a secure
mode with IP protection enabled. In such cases, access to Bank0 will return an error response
(3) Although the SRAM is mapped to both Code and System spaces, accesses from DMA to SRAM must
use the System space addressing ONLY.
6.5.2 Memory Map Access Response
The following table consolidates the access responses to the entire memory map of the MSP432P401x
devices.
ADDRESS RANGE
0x0000_0000–0x0003_FFFF
0x0004_0000–0x001F_FFFF
0x0020_0000–0x0020_3FFF
0x0020_4000–0x00FF_FFFF
0x0100_0000–0x0100_FFFF
0x0101_0000–0x01FF_FFFF
0x0200_0000–0x0200_03FF
0x0200_0400–0x0200_7FFF
0x0200_8000–0x1FFF_FFFF
0x2000_0000–0x2000_FFFF
0x2001_0000–0x21FF_FFFF
0x2200_0000–0x23FF_FFFF
0x2400_0000–0x3FFF_FFFF
0x4000_0000–0x4001_FFFF
0x4002_0000–0x41FF_FFFF
0x4200_0000–0x43FF_FFFF
0x4400_0000–0xDFFF_FFFF
Table 6-10. Memory Map Access Response
DESCRIPTION
Flash Main Memory
Reserved
Flash Information Memory
Reserved
SRAM
Reserved
ROM (Reserved)
ROM
Reserved
SRAM
Reserved
SRAM bit-band alias
Reserved
Peripheral
Reserved
Peripheral bit-band alias
Reserved
READ ⁽¹⁾
OK
Error
OK
Error
OK
Error
Error
OK
Error
OK
Error
OK ⁽⁴⁾
Error
OK
Error
OK ⁽⁴⁾
Error
WRITE ⁽¹⁾
OK ⁽²⁾, ⁽³⁾
Error
OK ⁽³⁾
Error
OK
Error
Error
Error
Error
OK
Error
OK
Error
OK
Error
OK
Error
INSTRUCTION
FETCH ⁽¹⁾
OK
Error
OK
Error
OK
Error
Error
OK
Error
OK
Error
Error
Error
Error
Error
Error
Error
(1) A 'reserved' memory region returns 0h on reads and instruction fetches. Writes to this region are ignored.
(2) If the User memory address is part of a secure region, this access returns an error if it is initiated by an unauthorized source. For more
details, refer to the device security application note.
(3) Writes to this address are ignored if the concerned sector has write protection enabled.
(4) Reads from the bit-band region return 00h if the bit is clear and 01h if the bit is set.
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