MSP432P401R Datasheet, PDF (88/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
NOTE
The glitch filter is implemented on the following digital I/Os on MSP432P401x devices: P1.0,
P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
6.8.1.1.1 Digital I/O Glitch Filter Control Register [Address = E004_0030h]
Figure 6-14. SYS_DIO_GLTFLT_CTL Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
GLTFL
T_EN
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw-1
BIT
31-1
0
FIELD
Reserved
GLTFLT_EN
Table 6-18. SYS_DIO_GLTFLT_CTL Register Description
TYPE
R
RW
RESET
0h
1h
DESCRIPTION
Reserved. Always reads 0h.
0b = Disables glitch filter on the digital I/Os.
1b = Enables glitch filter on the digital I/Os.
6.8.2 Port Mapping Controller (PMAPCTL)
The port mapping controller allows flexible and reconfigurable mapping of digital functions.
6.8.2.1 Port Mapping Definitions
The port mapping controller on MSP432P401x devices allows reconfigurable mapping of digital functions
over ports P2, P3, and P7.
VALUE
0
1
2
3
4
5
6
7
8
9
10
11
Table 6-19. Port Mapping, Mnemonics, and Functions
PxMAPy MNEMONIC
PM_NONE
PM_UCA0CLK
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCB0CLK
PM_UCB0SDA
PM_UCB0SIMO
PM_UCB0SCL
PM_UCB0SOMI
PM_UCA1STE
PM_UCA1CLK
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA2STE
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
None
DVSS
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 I²C data (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B0 I²C clock (open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
88
Detailed Description
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