MSP432P401R Datasheet, PDF (85/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
6.7.2.2 Supply Supervisor and Monitor for High Side (SVSMH)
The SVSMH supervises and monitors the V_CC. SVSMH has a programmable threshold setting and can be
used by the application to generate a reset or an interrupt if the V_CC dips below the desired threshold. In
supervisor mode, the SVSMH generates a device reset (POR class reset). In monitor mode, the SVSMH
generates an interrupt. The SVSMH can also be disabled if monitoring and supervision of the supply
voltage are not required (offers further power savings).
6.7.2.3 Core Voltage Regulator
The MSP432P401x devices can be programmed to operate either with an LDO or with a DC-DC as the
voltage regulator for the digital logic in the core domain of the device. The DC-DC offers significant boost
in power efficiency for high-current high-performance applications. The LDO is a highly efficient regulator
that offers power advantages at lower V_CC ranges and in the ultra-low-power modes of operation.
The core operating voltage (output of the LDO or DC-DC) is automatically set by the device depending on
the selected operating mode of the device (refer to Table 6-16 for further details). The device offers
seamless switching between LDO and DC-DC operating modes and also implements a seamless DC-DC
fail-safe mechanism.
6.7.2.4 Supply Supervisor for Low Side (SVSL)
The SVSL monitors the low-side (core domain) voltage of the device (also available at the VCORE pin). If
the core voltage drops below the trip threshold of the SVSL, the SVSL generates a device reset (POR
class reset). The SVSL can also be disabled if supervision of the core voltage is not required (offers
further power savings).
6.7.3 Power Control Manager (PCM)
The PCM controls the operating modes of the device and the switching between the modes. This is
controlled by the application, which can choose modes to meet its power and performance requirements.
Table 6-16 lists the operating modes of the device.
Table 6-16. MSP432P401x Operating Modes
OPERATING MODE
AM_LDO_VCORE0
LPM0_LDO_VCORE0
AM_LDO_VCORE1
LPM0_LDO_VCORE1
AM_DCDC_VCORE0
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
LPM0_DCDC_VCORE1
AM_LF_VCORE0
LPM0_LF_VCORE0
AM_LF_VCORE1
LPM0_LF_VCORE1
LPM3_VCORE0
LPM3_VCORE1
LPM4_VCORE0
LPM4_VCORE1
LPM3.5
LPM4.5
DESCRIPTION
LDO based active mode, medium performance, core voltage level 0
Same as above, except that CPU is OFF (no code execution)
LDO based active mode, maximum performance, core voltage level 1
Same as above, except that CPU is OFF (no code execution)
DC-DC based active mode, medium performance, core voltage level 0
Same as above, except that CPU is OFF (no code execution)
DC-DC based active mode, maximum performance, core voltage level 1
Same as above, except that CPU is OFF (no code execution)
LDO based low frequency active mode, core voltage level 0
Same as above, except that CPU is OFF (no code execution)
LDO based low frequency active mode, core voltage level 1
Same as above, except that CPU is OFF (no code execution)
LDO based low-power mode with full state retention, core voltage level 0, RTC and WDT can be active
LDO based low-power mode with full state retention, core voltage level 1, RTC and WDT can be active
LDO based low-power mode with full state retention, core voltage level 0, all peripherals disabled.
LDO based low-power mode with full state retention, core voltage level 1, all peripherals disabled
LDO based low-power mode, core voltage level 0, no retention of peripheral registers, RTC and WDT can be
active
Core voltage turned off, wake-up only through Pin Reset or Wake-up capable I/O's
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Detailed Description
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