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MSP432P401R Datasheet, PDF (71/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers
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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
6.3.2.3.1 SRAM Size Register (Address = 0xE004_3010h)
This register reflects the size of the SRAM available on the device.
Figure 6-8. SYS_SRAM_SIZE Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SIZE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
BIT
31-0
FIELD
SIZE
Table 6-5. SYS_SRAM_SIZE Register Description
TYPE
R
RESET
Variable
DESCRIPTION
Indicates the size (in bytes) of SRAM present on the device.
NOTE
The SRAM on the MSP432P401x devices is divided into equal size banks of 8KB each. For
example, if the total SRAM available is 32KB, the device contains 4 SRAM banks.
6.3.2.3.2 SRAM Bank Enable Register (Address = E004_3014h)
This register configures which bank of the SRAM is powered up and available for the application. The
application can choose to enable or disable SRAM banks on the fly. While the SRAM banks are being
powered up or down, accesses to the SRAM space is temporarily stalled and is completed when the
SRAM banks are ready. Accesses to the rest of the memory map remain unaffected.
Figure 6-9. SYS_SRAM_BANKEN Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
SRAM
_RDY
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r-0
15
14
13
12
11
10
9
Reserved
r
r
r
r
r
r
r
8
7
6
5
4
3
2
1
0
BNK7_ BNK6_ BNK5_ BNK4_ BNK3_ BNK2_ BNK1_ BNK0_
EN EN EN EN EN EN EN EN
r rw-<1> rw-<1> rw-<1> rw-<1> rw-<1> rw-<1> rw-<1> r-1
BIT
31-17
16
FIELD
Reserved
SRAM_RDY (1)
15-8
Reserved
Table 6-6. SYS_SRAM_BANKEN Register Description
TYPE
R
R
RESET
0h
0h
DESCRIPTION
Reserved. Reads return 0h
1b = SRAM is ready for accesses. All SRAM banks are enabled or disabled
according to values of bits 7:0 of this register
R
0h
0b = SRAM is not ready for accesses. Banks are undergoing the enable/disable
sequence, and reads/Writes to SRAM will be stalled until the banks are ready
Reserved. Reads return 0h
(1) This bit will automatically be set to 0 whenever any of the Bank Enable bits in this register are changed, which will in turn trigger off a
power up/down of the impacted SRAM blocks. It will set back to 1 after the power sequence is complete and the SRAM blocks are ready
for subsequent read/write accesses
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