MSP432P401R Datasheet, PDF (7/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
P10.1/UCB3CLK
P10.2/UCB3SIMO/UCB3SDA
P10.3/UCB3SOMI/UCB3SCL
P1.0/UCA0STE
P1.1/UCA0CLK
P1.2/UCA0RXD/UCA0SOMI
P1.3/UCA0TXD/UCA0SIMO
P1.4/UCB0STE
P1.5/UCB0CLK
P1.6/UCB0SIMO/UCB0SDA
P1.7/UCB0SOMI/UCB0SCL
VCORE
DVCC1
VSW
DVSS1
P2.0/PM_UCA1STE
P2.1/PM_UCA1CLK
P2.2/PM_UCA1RXD/PM_UCA1SOMI
P2.3/PM_UCA1TXD/PM_UCA1SIMO
P2.4/PM_TA0.1
P2.5/PM_TA0.2
P2.6/PM_TA0.3
P2.7/PM_TA0.4
P10.4/TA3.0/C0.7
P10.5/TA3.1/C0.6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P9.3/TA3.4
P9.2/TA3.3
DVCC2
DVSS2
P5.7/TA2.2/VREF-/VeREF-/C1.6
P5.6/TA2.1/VREF+/VeREF+/C1.7
P5.5/A0
P5.4/A1
P5.3/A2
P5.2/A3
P5.1/A4
P5.0/A5
P4.7/A6
P4.6/A7
P4.5/A8
P4.4/HSMCLK/SVMHOUT/A9
P4.3/MCLK/RTCCLK/A10
P4.2/ACLK/TA2CLK/A11
P4.1/A12
P4.0/A13
P6.1/A14
P6.0/A15
P9.1/A16
P9.0/A17
P8.7/A18
Notes:
1. The secondary digital functions on Ports P2, P3, and P7 are fully mappable. The pin designation shows only the
default mapping. See Table 6-19 for details.
2. Glitch filter is implemented on the following 8 digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
3. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
4. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
5. I²C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-1. 100-Pin PZ Package (Top View)
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Terminal Configuration and Functions
7
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