MSP432P401R Datasheet, PDF (43/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
Table 5-34. Digital Outputs, Normal I/Os
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V_OH
High-level output voltage
V_OL
Low-level output voltage
TEST CONDITIONS
I_(OHmax) = –1 mA ⁽¹⁾
I_(OHmax) = –3 mA ⁽²⁾
I_(OHmax) = –2 mA⁽¹⁾
I_(OHmax) = –6 mA⁽²⁾
I_(OLmax) = 1 mA ⁽¹⁾
I_(OLmax) = 3 mA ⁽²⁾
I_(OLmax) = 2 mA ⁽¹⁾
I_(OLmax) = 6 mA ⁽²⁾
V_CC
2.2 V
3.0 V
2.2 V
3.0 V
MIN
V_CC – 0.25
V_CC – 0.60
V_CC – 0.25
V_CC – 0.60
V_SS
V_SS
V_SS
V_SS
MAX
V_CC
V_CC
V_CC
V_CC
V_SS + 0.25
V_SS + 0.60
V_SS + 0.25
V_SS + 0.60
UNIT
V
V
1.62 V
20
f_Px.y
Port output frequency (with RC
load) ⁽³⁾
VCORE = 1.4 V, C_L = 20 pF, R_L ^{(4) (5)}
2.2 V
24
3.0 V
24
MHz
d_Px.y
Port output duty cycle (with RC
Load)
VCORE = 1.4 V, C_L = 20 pF, R_L ^{(4) (5)}
1.62 V
2.2 V
3.0 V
40%
40%
45%
60%
60%
55%
1.62 V
20
f_{Port_CLK} Clock output frequency⁽³⁾
VCORE = 1.4 V, C_L = 20 pF⁽⁵⁾
2.2 V
24
3.0 V
24
MHz
d_{Port_CLK} Clock output duty cycle
VCORE = 1.4 V, C_L = 20 pF⁽⁵⁾
1.62 V
2.2 V
3.0 V
40%
40%
45%
60%
60%
55%
t_rise,dig
Port output rise time, digital only
port pins
C_L = 20 pF ⁽⁶⁾
1.62 V
2.2 V
3.0 V
8
5 ns
3
t_fall,dig
Port output fall time, digital only
port pins
C_L = 20 pF ⁽⁷⁾
1.62 V
2.2 V
3.0 V
8
5 ns
3
t_rise,ana
Port output rise time, port pins
with shared analog functions
C_L = 20 pF ⁽⁶⁾
1.62 V
2.2 V
3.0 V
8
5 ns
3
t_fall,ana
Port output fall time, port pins
with shared analog functions
C_L = 20 pF ⁽⁷⁾
1.62 V
2.2 V
3.0 V
8
5 ns
3
(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) The port can output frequencies at least up to the specified limit - it might support higher frequencies.
(4) A resistive divider with 2 × R1 and R1 = 3.2kΩ between V_CC and V_SS is used as load. The output is connected to the center tap of the
divider. C_L = 20pF is connected to the output to V_SS.
(5) The output voltage reaches at least 20% and 80% V_CC at the specified toggle frequency.
(6) Measured between 20% of V_CC to 80% of V_CC.
(7) Measured between 80% of V_CC to 20% of V_CC.
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Specifications
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