MSP432P401R Datasheet, PDF (76/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Table 6-8. DMA Sources
SRCCFG = 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRCCFG = 1 SRCCFG = 2 SRCCFG = 3 SRCCFG = 4 SRCCFG = 5
eUSCI_A0 TX eUSCI_B0 TX0 eUSCI_B3 TX1 eUSCI_B2 TX2 eUSCI_B1 TX3
eUSCI_A0 RX eUSCI_B0 RX0 eUSCI_B3 RX1 eUSCI_B2 RX2 eUSCI_B1 RX3
eUSCI_A1 TX eUSCI_B1 TX0 eUSCI_B0 TX1 eUSCI_B3 TX2 eUSCI_B2 TX3
eUSCI_A1 RX
eUSCI_A2 TX
eUSCI_A2 RX
eUSCI_B1 RX0 eUSCI_B0 RX1 eUSCI_B3 RX2 eUSCI_B2 RX3
eUSCI_B2 TX0 eUSCI_B1 TX1 eUSCI_B0 TX2 eUSCI_B3 TX3
eUSCI_B2 RX0 eUSCI_B1 RX1 eUSCI_B0 RX2 eUSCI_B3 RX3
eUSCI_A3 TX eUSCI_B3 TX0 eUSCI_B2 TX1 eUSCI_B1 TX2 eUSCI_B0 TX3
eUSCI_A3 RX eUSCI_B3 RX0 eUSCI_B2 RX1 eUSCI_B1 RX2 eUSCI_B0 RX3
SRCCFG = 6
TA0CCR0
TA0CCR2
TA1CCR0
TA1CCR2
TA2CCR0
TA2CCR2
TA3CCR0
TA3CCR2
SRCCFG = 7
AES256_Trigge
r0
AES256_Trigge
r1
AES256_Trigge
r2
Reserved
Reserved
Reserved
DMAE0
(External Pin)
ADC14
NOTE
Any source marked as Reserved is unused. It may be used for software-controlled DMA
tasks, but typically it is reserved for enhancement purposes on future devices.
6.4.2 DMA Completion Interrupts
In the case of the ARM µDMA controller, it is usually the responsibility of software to maintain a list of
channels that have completed their operation. In order to provide further flexibility, the MSP432P401x
DMA supports four DMA completion interrupts, which are mapped in the following way:
• DMA_INT0: Logical OR of all completion events except those that are already mapped to DMA_INT1,
DMA_INT2, or DMA_INT3.
• DMA_INT1, DMA_INT2, DMA_INT3: Can be mapped to the DMA completion event of any of the eight
channels
NOTE
Software must ensure that DMA_INT1, DMA_INT2, and DMA_INT3 are mapped to different
channels, so that the same channel does not result in multiple interrupts at the NVIC.
6.4.3 DMA Access Privileges
The DMA has access to all the memories and peripheral configuration interfaces of the device. In the
event the device is configured for IP protection, DMA access to the flash is restricted to only the lower half
(second bank) of the flash main and information memory regions. This prevents the DMA from being used
as an unauthorized access source into the top half (first bank) of the flash, where secure data regions are
housed.
6.5 Memory Map Access Details
The bus system on the MSP432P401x devices incorporates 4 masters, which can initiate various types of
transactions
• ICODE: Cortex-M4 instruction fetch bus. Accesses the Code Zone only
• DCODE: Cortex-M4 data and literal fetch bus. Accesses the Code Zone only. Debugger accesses to
Code Zone also appear on this bus.
• SBUS: Cortex-M4 data read and write bus. Accesses to all zones except Code Zones and PPB
memory space only. Debugger accesses to this space also appear on this bus.
• DMA: Access to all zones except the PPB memory space
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Detailed Description
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