MSP432P401R Datasheet, PDF (27/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
5.10.2 Reset Timing
Table 5-15. Reset Recovery Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾
PARAMETER
MIN
TYP
MAX
t_SOFT
Latency from release of soft reset to first CPU instruction fetch
5
t_HARD
Latency from release of hard reset to release of soft reset
t_POR
Latency from release of device POR to release of hard reset
t_{COLDPWR,100 nF}
Latency from a cold power-up condition to release of device
POR, C_VCORE = 100 nF
t_{COLDPWR,4.7 µF}
Latency from a cold power-up condition to release of device
POR, C_VCORE = 4.7 µF
(1) Refer to Section 6.7.1 for details on the various classes of resets on the device
25
15
25
410
1000
530
1600
UNIT
MCLK
cycles
MCLK
cycles
µs
µs
µs
Table 5-16. External Reset (RSTn) Recovery Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
t_{AMLDO0_RSTn, 16MHz}
External reset applied on RSTn pin while the device is in
AM_LDO_VCORE0 mode with MCLK = 16 MHz,
The latency is from release of external reset to start of application code
TBD
t_{AMLDO1_RSTn, 32MHz}
External reset applied on RSTn pin while the device is in
AM_LDO_VCORE1 mode with MCLK = 32 MHz,
The latency is from release of external reset to start of application code
TBD
t_{AMLDO1_RSTn, 48MHz}
External reset applied on RSTn pin while the device is in
AAM_LDO_VCORE1 mode with MCLK = 48 MHz,
The latency is from release of external reset to start of application code
TBD
t_{AMDCDC0_RSTn, 16MHz}
External reset applied on RSTn pin while the device is in
AM_DCDC_VCORE0 mode with MCLK = 16 MHz,
The latency is from release of external reset to start of application code
TBD
t_{AMDCDC1_RSTn, 48MHz}
External reset applied on RSTn pin while the device is in
AM_DCDC_VCORE1 mode with MCLK = 48 MHz,
The latency is from release of external reset to start of application code
TBD
t_{AMLF0_RSTn, 128kHz}
External reset applied on RSTn pin while the device is in
AM_LF_VCORE0 mode with MCLK = 128 kHz from REFO,
The latency is from release of external reset to start of application code
TBD
t_{AMLF0_RSTn, 32kHz}
External reset applied on RSTn pin while the device is in
AM_LF_VCORE0 mode with MCLK = 32 kHz from LFXT,
The latency is from release of external reset to start of application code
TBD
t_{AMLF1_RSTn, 128kHz}
External reset applied on RSTn pin while the device is in
AM_LF_VCORE1 mode with MCLK = 128 kHz from REFO,
The latency is from release of external reset to start of application code
TBD
t_{LPM0LDO0_RSTn, 16MHz}
External reset applied on RSTn pin while the device is in
LPM0_LDO_VCORE0 mode with MCLK = 16 MHz,
The latency is from release of external reset to start of application code
TBD
t_{LPM0LDO1_RSTn, 48MHz}
External reset applied on RSTn pin while the device is in
LPM0_LDO_VCORE1 mode with MCLK = 48 MHz,
The latency is from release of external reset to start of application code
TBD
External reset applied on RSTn pin while the device is in
t_{LPM0DCDC0_RSTn, 16MHz} LPM0_DCDC_VCORE0 mode with MCLK = 16 MHz,
The latency is from release of external reset to start of application code
TBD
External reset applied on RSTn pin while the device is in
t_{LPM0DCDC1_RSTn, 48MHz} LPM0_DCDC_VCORE1 mode with MCLK = 48 MHz,
The latency is from release of external reset to start of application code
TBD
t_{LPM0LF0_RSTn, 128kHz}
External reset applied on RSTn pin while the device is in
LPM0_LF_VCORE0 mode with MCLK = 128 kHz from REFO,
The latency is from release of external reset to start of application code
TBD
MAX UNIT
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
4 ms
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
27