MSP432P401R Datasheet, PDF (79/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
6.6.1.1 NMI Control and Status Register [Address = E004_3004h]
Figure 6-12. SYS_NMI_CTLSTAT Register
31
30
29
28
27
26
Reserved
r
r
r
r
r
r
23
22
21
20
19
18
Reserved
PIN_FLG
PCM_FLG
r
r
r
r
rw-0
r-0
15
14
13
12
11
10
Reserved
r
r
r
r
r
r
7
6
5
4
3
2
Reserved
PIN_SRC
PCM_SRC
r
r
r
r
rw-0
rw-1
25
r
17
PSS_FLG
r-0
9
r
1
PSS_SRC
rw-1
24
r
16
CS_FLG
r-0
8
r
0
CS_SRC
rw-1
Table 6-11. SYS_NMI_CTLSTAT Register Description
BIT
31-20
19
FIELD
Reserved
PIN_FLG
TYPE
R
RW
RESET
0h
0h
DESCRIPTION
Reserved. Reads return 0h
0b = Indicates the RSTn/NMI pin was not the source of NMI
18
PCM_FLG
1b = Indicates the RSTn/NMI pin was the source of NMI
R
0h
0b = Indicates the PCM interrupt was not the source of NMI
1b = Indicates the PCM interrupt was the source of NMI
17
PSS_FLG
This flag gets auto-cleared when the corresponding source flag in the PCM is
cleared
R
0h
0b = Indicates the PSS interrupt was not the source of NMI
1b = Indicates the PSS interrupt was the source of NMI
16
CS_FLG
This flag gets auto-cleared when the corresponding source flag in the PSS is
cleared
R
0h
0b = Indicates CS interrupt was not the source of NMI
1b = Indicates CS interrupt was the source of NMI
15-4
3
Reserved
PIN_SRC ^{(1) (2)}
R
0h
RW
0h
This flag gets auto-cleared when the corresponding source flag in the CS is
cleared
Reserved. Reads return 0h
0b = Configures the RSTn/NMI pin as a source of POR Class Reset
1b = Configures the RSTn/NMI pin as a source of NMI
Note: Setting this bit to 1 prevents the RSTn pin from being used as a reset.
2
PCM_SRC
RW
1h
An NMI is triggered by the pin only if a negative edge is detected.
0b = Disbles the PCM interrupt as a source of NMI
1
PSS_SRC
RW
1h
1b = Enables the PCM interrupt as a source of NMI
0b = Disables the PSS interrupt as a source of NMI
1b = Enables the PSS interrupt as a source of NMI
(1) When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit will be retained. If selected as an NMI,
activity on this pin in LPM3/LPM4 will wake the device and process the interrupt, without causing a POR. If selected as a Reset, activity
on this pin in LPM3/LPM4 will cause a device level POR
(2) When the device enters LPM3.5/LPM4.5 modes of operation, this bit will always be cleared to 0. In other words, the RSTn/NMI pin will
always assume a reset functionality in LPM3.5/LPM4.5 modes.
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Detailed Description
79