MSP432P401R Datasheet, PDF (133/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
Table 6-51. Port PJ (PJ.0 and PJ.1) Pin Functions
PIN NAME (PJ.x) x
FUNCTION
PJDIR.x
CONTROL BITS OR SIGNALS ⁽¹⁾
PJSEL1.1 PJSEL0.1 PJSEL1.0 PJSEL0.0
LFXT
BYPASS
PJ.0/LFXIN
0 PJ.0 (I/O)
I: 0; O: 1
X
X
0
0
X
N/A
DVSS
0
X
X
1
X
X
1
LFXIN crystal mode ⁽²⁾
X
X
X
0
1
0
LFXIN bypass mode ⁽²⁾
X
X
X
0
1
1
PJ.1/LFXOUT
1
PJ.1 (I/O)
0
0
0
I: 0; O: 1
0
0
1
X
X
X
1 ⁽³⁾
0
0
N/A
0
see ⁽⁴⁾
see ⁽⁴⁾
1
X
0
X
X
1 ⁽³⁾
DVSS
0
1
see ⁽⁴⁾
see ⁽⁴⁾
1
X
LFXOUT crystal mode ⁽²⁾
X
X
X
0
0
0
X
X
1 ⁽³⁾
1
0
(1) X = Don't care
(2) Setting PJSEL1.0 = 0 and PJSEL0.0 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.0 and PJ.1 are
configured for crystal operation and PJSEL1.1 and PJSEL0.1 are do not care. When LFXTBYPASS = 1, PJ.0 is configured for bypass
operation and PJ.1 is configured as general-purpose I/O.
(3) When PJ.0 is configured in bypass mode, PJ.1 is configured as general-purpose I/O.
(4) With PJSEL0.1 = 1 or PJSEL1.1 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
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Detailed Description 133