MSP432P401R Datasheet, PDF (19/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
5.9 Current Consumption
Table 5-1. Current Consumption During Device Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ^(1)(2)(3)
I_RESET
PARAMETER
V_CC
2.2 V
3.0 V
TYP
MAX
540
1300
(1) Device held in reset through RSTn/NMI pin.
(2) Current measured into V_CC.
(3) All other input pins tied to 0 V or V_CC. Outputs do not source or sync any current.
UNIT
µA
Table 5-2. Current Consumption in LDO-Based Active Modes
over recommended operating free-air temperature (unless otherwise noted)^{(1)(2)(3)(4)(5)}
PARAMETER
EXECUTION
MEMORY
V_CC
MCLK =
8 MHz
TYP MAX
MCLK =
16 MHz
TYP MAX
MCLK =
24 MHz
TYP MAX
MCLK =
32 MHz
TYP MAX
MCLK =
40 MHz
TYP MAX
I_{AM_LDO_VCORE0,Flash} ^{(6) (7)}
I_{AM_LDO_VCORE1,Flash} ^{(6) (7)}
I_{AM_LDO_VCORE0,SRAM} ⁽⁸⁾
I_{AM_LDO_VCORE1,SRAM} ⁽⁸⁾
Flash
Flash
SRAM
SRAM
3.0 V
3.0 V
3.0 V
3.0 V
3950 4700
(1) MCLK sourced by DCO.
(2) Current measured into V_CC.
(3) All other input pins tied to 0 V or V_CC. Outputs do not source or sync any current.
(4) All SRAM banks kept active.
(5) All peripherals are inactive.
(6) Device executing the Dhrystone 2.1 algorithm. Code execution from Flash, stack and data in SRAM.
(7) Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8) Device executing the Dhrystone 2.1 algorithm. Code execution from SRAM, stack and data in SRAM.
MCLK =
48 MHz
UNIT
TYP MAX
µA
7600 8500 µA
µA
µA
Table 5-3. Current Consumption in DC-DC-Based Active Modes
over recommended operating free-air temperature (unless otherwise noted)^{(1)(2)(3)(4)(5)}
PARAMETER
EXECUTION
MEMORY
V_CC
MCLK =
8 MHz
TYP MAX
MCLK =
16 MHz
TYP MAX
MCLK =
24 MHz
TYP MAX
MCLK =
32 MHz
TYP MAX
MCLK =
40 MHz
TYP MAX
I_{AM_DCDC_VCORE0,Flash} ^{(6) (7)}
I_{AM_DCDC_VCORE1,Flash} ^{(6) (7)}
I_{AM_DCDC_VCORE0,SRAM} ⁽⁸⁾
I_{AM_DCDC_VCORE1,SRAM} ⁽⁸⁾
Flash
Flash
SRAM
SRAM
3.0 V
3.0 V
3.0 V
3.0 V
2200 2800
(1) MCLK sourced by DCO.
(2) Current measured into V_CC.
(3) All other input pins tied to 0 V or V_CC. Outputs do not source or sync any current.
(4) All SRAM banks kept active.
(5) All peripherals are inactive.
(6) Device executing the Dhrystone 2.1 algorithm. Code execution from Flash, stack and data in SRAM.
(7) Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8) Device executing the Dhrystone 2.1 algorithm. Code execution from SRAM, stack and data in SRAM.
MCLK =
48 MHz
UNIT
TYP MAX
µA
4600 5400 µA
µA
µA
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Specifications
19