MSP432P401R Datasheet, PDF (82/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
6.7 System Control
System Control comprises the modules that govern the overall behavior of the device, including power
management, operating modes, clocks, reset handling, and user configuration settings.
6.7.1 Device Resets
The MSP432P401x devices support multiple classes of reset. Each class results in a different level of
initiation of device logic, thus offering the application developer the capability of initiating different resets
based reset requirements during code development and debug. The following subsections cover the
classes of reset in the device
6.7.1.1 Power On/Off Reset (POR)
The POR initiates a complete initialization of the application settings and device configuration information.
This class of reset may be initiated either by the PSS, the PCM, the RSTn pin, the Clock System upon
DCO external resistor short circuit fault or the device emulation logic (through the debugger). From an
application perspective, all sources of POR return the device to the same state of initialization.
NOTE
Depending on the source of the reset, the device may exhibit different wake-up latencies
from the POR. This implementation enables optimization of the reset recovery time.
6.7.1.2 Reboot Reset
The Reboot Reset is identical to the POR, and allows the application to emulate a POR class reset
without needing to power cycle the device or activating the RSTn pin. It can also be initiated through the
debugger, and hence does not affect the debug connection to the device. On the other hand, a POR will
result in a debug disconnect.
6.7.1.2.1 Reboot Control Register (Address = E004_3000h)
Figure 6-13. SYS_REBOOT_CTL Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WKEY
Reserved
REBO
OT
w
w
w
w
w
w
w
w
r
r
r
r
r
r
r
w
BIT
31-16
15-8
7-1
0
FIELD
Reserved
WKEY
Reserved
REBOOT
Table 6-13. SYS_REBOOT_CTL Register Description
TYPE
R
W
R
W
RESET
0h
0h
0h
0h
DESCRIPTION
Reserved. Reads return 0h
Key to enable writes to bit 0. Bit 0 is written only if WKEY is 69h in the same
write cycle
Reserved. Reads return 0h
Write 1 initiates a Reboot of the device
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Detailed Description
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