MSP432P401R Datasheet, PDF (10/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
4.2 Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
TERMINAL
NAME
PZ
P10.1/
UCB3CLK
1
P10.2/
UCB3SIMO/UCB3SDA
2
P10.3/
UCB3SOMI/UCB3SCL
3
P1.0/
UCA0STE
4
P1.1/
UCA0CLK
5
P1.2/
UCA0RXD/UCA0SOMI
6
P1.3/
UCA0TXD/UCA0SIMO
7
P1.4/
UCB0STE
8
P1.5/
UCB0CLK
9
P1.6/
UCB0SIMO/UCB0SDA
10
P1.7/
UCB0SOMI/UCB0SCL
11
VCORE ⁽³⁾
12
DVCC1
13
VSW
14
DVSS1
15
P2.0/
PM_UCA1STE
16
P2.1/
PM_UCA1CLK
17
P2.2/
PM_UCA1RXD/
18
PM_UCA1SOMI
Table 4-1. Signal Descriptions
NO. ⁽²⁾
ZXH RGC
N/A N/A
N/A N/A
N/A N/A
A1
1
B1
2
C4
3
D4
4
D3
5
C1
6
D1
7
E1
8
C2
9
D2 10
E2
11
F2
12
E4
13
F1
14
E3
15
I/O ⁽¹⁾
DESCRIPTION
General-purpose digital I/O
I/O Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
General-purpose digital I/O
I/O Slave in, master out – eUSCI_B3 SPI mode
I²C data – eUSCI_B3 I²C mode
General-purpose digital I/O
I/O Slave out, master in – eUSCI_B3 SPI mode
I²C clock – eUSCI_B3 I²C mode
General-purpose digital I/O with port interrupt, wake-up and glitch filtering
I/O capability
Slave transmit enable – eUSCI_A0 SPI mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_Ao0 SPI master mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Receive data – eUSCI_A0 UART mode
Slave out, master in – eUSCI_A0 SPI mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Transmit data – eUSCI_A0 UART mode
Slave in, master out – eUSCI_A0 SPI mode
General-purpose digital I/O with port interrupt, wake-up and glitch filtering
I/O capability
Slave transmit enable – eUSCI_B0 SPI mode
General-purpose digital I/O with port interrupt, wake-up and glitch filtering
I/O
capability
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Slave in, master out – eUSCI_B0 SPI mode
I²C data – eUSCI_B0 I²C mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Slave out, master in – eUSCI_B0 SPI mode
I²C clock – eUSCI_B0 I²C mode
Regulated core power supply (internal use only, no external current
loading)
Digital power supply
DC-to-DC converter switching output.
Digital ground supply
I/O
General-purpose digital I/O with port interrupt and wake-up capability
Slave transmit enable – eUSCI_A1 SPI mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
General-purpose digital I/O with port interrupt and wake-up capability
I/O Receive data – eUSCI_A1 UART mode
Slave out, master in – eUSCI_A1 SPI mode
(1) I = input, O = output
(2) N/A = not available
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C_VCORE.
10
Terminal Configuration and Functions
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