MSP432P401R Datasheet, PDF (87/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
6.7.5 System Controller (SYSCTL)
The SYSCTL is a set of various miscellaneous features of the device, including SRAM bank configuration,
RSTn/NMI function selection, and peripheral halt control. In addition, the SYSCTL enables device security
features like JTAG and SWD lock and IP protection, which can be used to protect unauthorized accesses
either to the entire device memory map or to certain selected regions of the flash. Table 6-17 lists the
registers that are part of SYSCTL. Only the offsets of the registers are listed—the entire addresses are
listed with the complete register definitions elsewhere this data sheet.
OFFSET
000h
004h
008h
00Ch
010h
014h
018h
020h
030h
ACRONYM
SYS_REBOOT_CTL
SYS_NMI_CTLSTAT
SYS_WDTRESET_CTL
SYS_PERIHALT_CTL
SYS_SRAM_SIZE
SYS_SRAM_BANKEN
SYS_SRAM_BANKRET
SYS_FLASH_SIZE
SYS_DIO_GLTFLT_CTL
Table 6-17. SYSCTL Registers
REGISTER NAME
Reboot Control Register
NMI Control and Status Register
Watchdog Reset Control Register
Peripheral Halt Control Register
SRAM Size Register
SRAM Bank Enable Register
SRAM Bank Retention Control Register
Flash Size Register
Digital I/O Glitch Filter Control Register
SECTION
Section 6.7.1.2.1
Section 6.6.1.1
Section 6.8.7.1
Section 6.9.2
Section 6.3.2.3.1
Section 6.3.2.3.2
Section 6.3.2.3.3
Section 6.3.1.1.1
Section 6.8.1.1.1
NOTE
As is the case with the Cortex-M4 system control registers (housed on the internal PPB
space), the System Controller module registers are mapped to the Cortex-M4 external PPB.
This keeps the System Controller module accessible even when the Hard and/or Soft resets
are active.
6.8 Peripherals
6.8.1 Digital I/O
There are up to 10 8-bit I/O ports implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt capability is available on ports P1 through P6.
• Wake-up capability from LPM3, LPM4, LPM3.5, and LPM4.5 modes over ports P1 through P6.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or in pairs (16bit widths).
• Capacitive Touch functionality is supported on all pins of ports P1 through P10 and PJ.
• Glitch filtering capability on selected digital I/Os.
6.8.1.1 Glitch Filtering on Digital I/Os
Some of the interrupt and wake-up capable digital I/Os have the capability to suppress glitches through
the use of analog glitch filter to prevent unintentional interrupt or wake-up during device operation. The
analog filter will suppress a minimum of 250ns wide glitches. The glitch filter on these selected digital I/Os
is enabled by default. If the glitch filtering capability is not required in the application there is a provision to
bypass them by programming the SYS_DIO_GLTFLT_CTL register. When GLTFLT_EN bit in this register
is cleared then glitch filters on all the digital I/Os are bypassed at once. The glitch filter is automatically
bypassed on a digital I/O when it is configured for peripheral or analog functionality by programming the
respective PySEL0.x, PySEL1.x registers.
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