MSP432P401R Datasheet, PDF (89/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
Table 6-19. Port Mapping, Mnemonics, and Functions (continued)
VALUE
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 (0FFh)⁽¹⁾
PxMAPy MNEMONIC
PM_UCA2CLK
PM_UCA2RXD
PM_UCA2SOMI
PM_UCA2TXD
PM_ UCA2SIMO
PM_UCB2STE
PM_UCB2CLK
PM_UCB2SDA
PM_UCB2SIMO
PM_UCB2SCL
PM_UCB2SOMI
PM_TA0.0
PM_TA0.1
PM_TA0.2
PM_TA0.3
PM_TA0.4
PM_TA1.1
PM_TA1.2
PM_TA1.3
PM_TA1.4
PM_TA0CLK
PM_C0OUT
PM_TA1CLK
PM_C1OUT
PM_DMAE0
PM_SMCLK
PM_ANALOG
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_B2 clock input/output (direction controlled by eUSCI)
eUSCI_B2 I²C data (open drain and direction controlled by eUSCI)
eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)
eUSCI_B2 I²C clock (open drain and direction controlled by eUSCI)
eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
TA1 CCR3 capture input CCI3A
TA1 CCR3 compare output Out3
TA1 CCR4 capture input CCI4A
TA1 CCR4 compare output Out4
Timer_A0 external clock input
None
None
Comparator-E0 output
Timer_A1 external clock input
None
None
Comparator-E1 output
DMAE0 input
None
None
SMCLK
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 31. The port mapping registers are 5 bits wide, and the upper bits are ignored, which
results in a read value of 31.
PIN NAME
P2.0/PM_UCA1STE
P2.1/PM_UCA1CLK
P2.2/PM_UCA1RXD/
PM_UCA1SOMI
P2.3/PM_UCA1TXD/
PM_UCA1SIMO
P2.4/PM_TA0.1 ⁽¹⁾
P2.5/PM_TA0.2 ⁽¹⁾
P2.6/PM_TA0.3 ⁽¹⁾
P2.7/PM_TA0.4 ⁽¹⁾
P3.0/PM_UCA2STE
P3.1/PM_UCA2CLK
P3.2/PM_UCA2RXD/
PM_UCA2SOMI
Table 6-20. Default Mapping
PxMAPy MNEMONIC
PM_UCA1STE
PM_UCA1CLK
PM_UCA1RXD/
PM_UCA1SOMI
PM_UCA1TXD/
PM_UCA1SIMO
PM_TA0.1
PM_TA0.2
PM_TA0.3
PM_TA0.4
PM_UCA2STE
PM_UCA2CLK
PM_UCA2RXD/
PM_UCA2SOMI
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
eUSCI_A1 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
eUSCI_A2 UART RXD (direction controlled by eUSCI – input)/
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
(1) Not available on the 64-pin RGC package.
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Detailed Description
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