MSP432P401R Datasheet, PDF (70/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
www.ti.com
6.3.2.1 SRAM Bank Enable Configuration
The application can choose to optimize the power consumption of the SRAM. In order to enable this, the
SRAM memory is divided into 8KB banks that can individually be powered down. Banks that are powered
down remain powered down in both active as well as low-power modes of operation, thereby limiting any
unnecessary inrush current when the device transitions between active and retention based low-power
modes. The application can also choose to disable one (or more) banks for a certain stage in the
processing and re-enable it for another stage. Refer to Section 6.3.2.3 for details on how individual banks
can be controlled by the application.
Whenever a particular bank is disabled, reads to its address space return 0h, and writes are discarded. To
prevent 'holes' in the memory map, if a particular bank is enabled, all the lower banks are forced to
enabled state as well. This ensures a contiguous memory map through the set of enabled banks instead
of a possible disabled bank appearing between enabled banks.
NOTE
Bank0 is always enabled and cannot be powered down.
NOTE
When any SRAM bank is enabled or disabled, accesses to the SRAM are temporarily stalled
to prevent spurious reads. This is handled transparently and does not require any code
intervention. Refer to SRAM characteristics in the electrical specification for the SRAM bank
enable or disable latency.
6.3.2.2 SRAM Bank Retention Configuration and Backup Memory
The application can choose to optimize the leakage power consumption of the SRAM in LPM3 and LPM4
modes of operation as well. In order to enable this, each SRAM bank can be individually configured for
retention. Banks that are enabled for retention retain their data through the LPM3 and LPM4 modes. The
application can also choose to retain a subset of the enabled banks.
For example, the application may need 32KB of SRAM for its processing needs (4 banks are kept
enabled). However, of these four banks, only one bank may contain critical data that must be retained in
LPM3 or LPM4 modes while the rest are powered off completely to minimize power consumption. Refer to
Section 6.3.2.3 for details on how individual banks can be controlled by the application.
Bank0 of SRAM is always retained and cannot be powered down. Therefore, it also operates up as a
possible backup memory in the LPM3, LPM4, and LPM3.5 modes of operation.
6.3.2.3 SRAM Status and Configuration Registers
This section lists the registers that can be used to configure and/or monitor status regarding the SRAM.
70
Detailed Description
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M