MSP432P401R Datasheet, PDF (15/157 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826B – MARCH 2015 – REVISED FEBRUARY 2016
5 Specifications
5.1 Absolute Maximum Ratings ⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at DVCC and AVCC pins to V_SS
Voltage difference between DVCC and AVCC pins⁽²⁾
–0.3
4.17
V
±0.3
V
Voltage applied to any pin⁽³⁾
–0.3
V_CC + 0.3 V
(4.17 V MAX)
V
Diode current at any device pin
Storage temperature, T_stg ⁽⁴⁾
Maximum junction temperature, T_J
±2
mA
–40
125
°C
95
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device.
(3) All voltages referenced to V_SS.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
V_(ESD) Electrostatic discharge _{Charged-device model (CDM), per JEDEC specification JESD22-C101(2)}
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
TYP data are based on V_CC = 3.0 V, T_A = 25°C (unless otherwise noted)
MIN
NOM
MAX UNIT
At power-up (with internal V_CC
supervision)
1.65
3.7
V_CC
V_SS
I_INRUSH
f_MCLK
T_A
T_J
Supply voltage range at all DVCC and
AVCC pins ^{(1) (2) (3)}
Normal operation, Flash not active (with
internal V_CC supervision)
Normal operation, Flash active (with
internal V_CC supervision)
Normal operation, Flash active (without
internal V_CC supervision)
Supply voltage on all DVSS and AVSS pins
Inrush current into the V_CC pins⁽⁴⁾
Frequency of the CPU and AHB clock in the system⁽⁵⁾
Operating free-air temperature
Operating junction temperature
1.62
1.71
1.62
0
–40
–40
3.7
V
3.7
3.7
0
V
100 mA
48 MHz
85 °C
95 °C
(1) TI recommends powering AV_CC and DV_CC from the same source. A maximum difference of ±0.1 V between AV_CC and DV_CC can be
tolerated during power up and operation. Refer to section Section 5.4 for decoupling capacitor recommendations.
(2) Supply voltage must not change faster than TBD. Faster changes can cause the VCCDET to trigger a reset even within the
recommended supply voltage range.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) Does not include I/O currents (driven by application requirements)
(5) Operating frequency may require the flash to be accessed with wait states. Refer to Section 5.8 for further details
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Specifications
15