DS92UT16TUF Datasheet, PDF (84/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

25.0 Appendix A: Layout and
Connection Guidelines (Continued)
25.1 POWER CONNECTIONS
25.1.1 Digital Supplies (DV_DD and DGND)
The digital supply pins provide power to the digital section of
the device. Since the digital supplies are subject to switching
noise, the bypass considerations are important. The DV_DD
and DGND balls are located mostly in the center of the ball
array. If the PCB stack-up and signal routing allows placing
bypass caps on the bottom of the board close to the digital
supply pins, then an array of capacitors will provide wide
band bypassing. The total bypass capacitance should be at
least 0.3 µF.
The 2.5V supply pins are located near the edge of the
package, which is more convenient for placement of bypass
capacitors. If a power plane supplies the 2.5V, then standard
bypass capacitors of 0.1 µF in parallel with 0.01 µF is suffi-
cient. If the PCB traces connect the 2.5V to the part, then
additional bulk decoupling capacitance should account for
the added trace inductance.
25.1.2 Analog Supplies (AV_DD and AGND)
The analog V_DD and GND power the LVDS driver and re-
ceiver section of the device. High frequency bypassing such
as 0.001 µF capacitance is required due to the very high
data rates of the LVDS signals. See Figure 34.
25.1.3 PLL Supplies (PV_DD and PGND)
The PLL supply pins provide power for the PLL(s) in the
circuit. The most important function of bypassing or filtering
for the PLL inputs is to attenuate low frequency noise from
entering the PV_DD pins. A common source of low frequency
noise is switching power supplies. Power distribution net-
works should be designed to attenuate any harmonics cre-
ated by the switching supply. The addition of a PI filter
network at the PV_DD pins is optional. See Figure 34.
25.2 LAYOUT GUIDELINES
25.2.1 Digital Supplies (DV_DD and DGND)
Digital supply connection to bypass capacitors can be diffi-
cult, but the more layers in the PCB the easier it is to place
the capacitors near the device. Therefore, the recommenda-
tion is to use full power planes to distribute power to these
pins. Using the minimum manufacturing thickness between
the ground and power planes creates a distributed bypass
capacitance. Due to the potentially high inrush currents
caused by Utopia bus output switching, using traces routed
through the array to connect bypass caps to the balls is not
recommended. This is because the inductance of the traces
will negate the affect of the bypass capacitors.
25.2.2 Analog Supplies (AV_DD and AGND)
In general, the analog supply pins can be connected to the
digital power planes. The AGND pins should be connected to
a ground plane that connects them directly to the AGND pins
of the sending device. This provides for minimum ground
offset between the devices and provides a return path for the
minute return currents from the LVDS receivers.
25.2.3 PLL Supplies (PV_DD and PGND)
The PLL supply pins should be isolated from the shared
digital and analog power planes. PV_DD and PGND pins are
generally grouped together to allow them to be connected to
a split plane or to a “copper pour” on the top layer. The split
plane or copper pour is connected to the power planes
through a PI filter to block low frequency noise. High fre-
quency bypassing should be provided on the PLL side of the
filter to supply switching current to the PLL. A separate filter
for each PLL is recommended. If filters are not desired use a
high value (5 µF to 400 nF) capacitor connected to the PV_DD
pins to limit low frequency noise.
25.2.4 LVDS I/O
The LVDS I/O pins are located on the outer ring of balls so
they can be routed on the surface layer to minimize added
capacitance. Use surface mount resistors to terminate trans-
mission lines as close to the LVDS inputs as possible. The
LVDS drivers on the DS92UT16 are designed to drive 100Ω
differential lines.
The LVDS A driver outputs (LVDS_Adin[+/−]) are swapped in
position compared to the other LVDS I/O pairs. This allows
them to be “wrapped around ” a connector pin array so that
all of the LVDS signals can be routed on the surface layer.
See Figure 35.
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