DS92UT16TUF Datasheet, PDF (29/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

14.0 Performance Monitoring (Continued)
Alarms
MTBHOVA (Section 18.72
UTOPIA AND ATM
ALARMS — 0xE1 UAA)
TABLE 15. General Alarms (Continued)
Description
MTB Hard overflow. The MTB queue has overflowed (up-bridge).
15.0 Loopback Operation
To assist in diagnostic testing, the DS92UT16 provides both
physical interface loopbacks and ATM cell loopbacks as
shown in Figure 7 in Section 6.8 LOOPBACKS. The former
is suitable for designer or commission testing when the
device is not passing live traffic. The latter allows cell trace
testing on live traffic. All loopbacks are programmable via the
microprocessor interface. The LVDS physical loopbacks are
described in Section 12.5 LOOPBACK TEST OPERATION.
15.1 ATM CELL LOOPBACK
The ATM Cell Loopback function provides two separate loop-
back operations. The Down2Up_ATM loopback detects spe-
cial loopback cells received on the UTOPIA interface and
transmits them back out over the UTOPIA interface. The
Up2Down_ATM loopback detects special loopback cells re-
ceived on the LVDS interface and transmits them back out
over the LVDS interface. Figure 7(b) in Section 6.8 LOOP-
BACKS illustrates both of these operations.
These loopback circuits accommodate one loopback cell at
a time. Therefore, a loopback cell should be sent and re-
ceived before transmitting another loopback cell.
The ATM and LVDS Loopback Control register ALBC con-
trols the ATM cell loopback functionality. See Section 18.14
GENERAL PURPOSE INPUT OUTPUT — 0x15 GPIO. Bit
D2ULB enables the Down2Up_ATM loopback and bit
U2DLB enables the Up2Down_ATM loopback. It is possible
to enable both loopback operations at the same time.
The special loopback cell format is defined in the ATM Loop-
back Cell Format registers ALBCF3–ALBCF0. See Section
18.20 ATM LOOPBACK CELL FORMAT — 0x1C to 0x1F
ALBCF3 to ALBCF0. These registers define the contents of
the cell’s four header bytes, which indicate that a received
cell is a loopback cell. Associated with the ALBCF3–ALBCF0
registers are the ATM Loopback Cell Filter registers
ALFLT3–ALFLT0. See Section 18.74 ATM LOOPBACK
CELL FILTER — 0xF7 to 0xFA ALFLT3 to AFLT0. These
registers define the cell header bits that are compared with
the header format declared in the ALBCF3–ALBCF0 regis-
ters. It is therefore possible to mask out any bits of the cell
header from comparison.
For Down2Up_ATM loopback on the UTOPIA interface only,
a loopback cell will be sent back out to the MPhy address on
which it was received. So, if a loopback cell was detected
coming into the device on MPhy address 0x01, then it will be
sent back out of the device on the next occasion that a cell
for MPhy address 0x01 is to be sent.
For Up2Down_ATM loopback on the LVDS interface, the
MPhy address is embedded in the incoming PDU. Therefore,
the loopback cell is simply transmitted back out.
For Down2Up_ATM loopback, only loopback cells as defined
by the ALBCF3–ALBCF0 and ALFLT3–ALFLT0 registers are
looped-back and all other cells are passed as normal.
For Up2Down_ATM loopback, only loopback cells as defined
by the ALBCF3–ALBCF0 and ALFLT3–ALFLT0 registers are
looped back and all other cells are passed as normal.
The Down2Up Loopback Cell Count register, the D2ULBCC
in Section 18.71 ATM DOWN2UP LOOPBACK CELL
COUNT — 0xE0 D2ULBCC, maintains a count of the
Down2UP_ATM loopback cells. Whenever this counter in-
crements, the D2ULBC alarm in the UAA register is set. See
Section 18.72 UTOPIA AND ATM ALARMS — 0xE1 UAA.
Note that this counter only increments when the loopback
cell exits the device. So the D2ULBC counter increments on
outgoing loopback cells.
Both Receive Port A and Receive Port B maintain
Up2Down_ATM loopback counts. The registers that main-
tain these counts are the Receive Port A Up2Down Loop-
back Cell Count register, RAU2DLBC, and the Receive Port
B Up2Down Loopback Cell Count register, RBU2DLBC. See
Section 18.35 RECEIVE PORT A UP2DOWN LOOPBACK
CELL COUNT — 0x3E RAU2DLBC and Section 18.54 RE-
CEIVE PORT B UP2DOWN LOOPBACK CELL
COUNT — 0x7E RBU2DLBC.
Whenever the counter in the Active receiver (as defined by
the LBA bit of the LKSC, see Section 18.8 LINK STATUS
AND CONTROL — 0x08 LKSC) increments, the U2DLBC
alarm in the UAA register is set. See Section 18.72 UTOPIA
AND ATM ALARMS — 0xE1 UAA. Although each counter
increments whenever it detect an incoming loopback cell,
only increments to the active receiver’s counter can set the
alarm. Note that received loopback cells increment these
counters. So the U2DLBC counter increments on incoming
loopback cells.
Alarms in the UAA register will raise an interrupt if the
appropriate interrupt enables are set in the UAIE register.
See Section 18.73 UTOPIA AND ATM INTERRUPT
ENABLES — 0xE2 UAIE.
Loopback cells are only counted and looped-back in the
appropriate loopback mode. If the loopback mode is not set
then any incoming loopback cells are simply treated as
normal traffic cells and passed by the device. In
Up2Down_ATM loopback mode, only cells from the Active
receiver will be looped-back.
A loopback cell transmission may be initiated by the
DS92UT16 over the LVDS transmit link. The TXLVLB bit in
the ALBC register controls this functionality. Setting the
TXLVLB bit causes a single loopback cell to be transmitted
over the LVDS transmit link. When the DS92UT16 finishes
transmitting the loopback cell, it automatically clears the
TXLVLB bit. So, the processor, on setting the TXLVLB bit,
should poll it to detect that it clears before trying to set it
again to send another loopback cell. The loopback cell trans-
mitted will have a header of the format defined by the
ALBCF3–ALBCF0 registers and an MPhy address as de-
fined by the ALBMP register
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