DS92UT16TUF Datasheet, PDF (15/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

8.0 UTOPIA Interface Operation (Continued)
FIGURE 8. Basic UTOPIA Level 2 UMODE Configuration
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8.1.1 ATM Polling
When configured as an ATM Layer device, the DS92UT16
polls the connected PHY ports using the MPhy address
busses U_TxAddr and U_RxAddr. Only those ports which
are connected will be polled. The connected ports list de-
fined in the UCPL3–UCPL0 registers is used to determine
which ports are connected. The PHY ports respond only on
U_TxCLAV[0] and U_RxCLAV[0]. On reset the
UCPL3–UCPL0 registers are all set to 0xFF so the
DS92UT16 will poll all ports.
8.1.2 PHY Polling
When configured as a PHY Layer device the DS92UT16 is
polled by the connected ATM device. During polling the
DS92UT16 will only respond to MPhy addresses, on
U_TxAddr and U_RxAddr, which are defined as connected.
The connected ports list defined in the UCPL3–UCPL0 reg-
isters is used to determine which ports are connected. On
reset the UCPL3–UCPL0 registers are all set to 0xFF so the
DS92UT16 will respond to all MPhy addresses during poll-
ing. The DS92UT16 responds only on U_TxCLAV[0] and
U_RxCLAV[0].
NOTE: There must always be at least one connected port
defined in the UCPL3–UCPL0 registers. If no ports are to be
connected then use Configuration Traffic Inhibit mode de-
scribed in Section 10.0 Configuration and Traffic Inhibit Op-
eration.
8.2 UTOPIA EXTENDED LEVEL 2 MODE - 248 PORTS
In UTOPIA Extended Level 2 mode:
• 8-bit or 16-bit data buses are controlled by the BWIDTH
bit of the UCFG register. In 8-bit mode, only
U_TxData[7:0] and U_RxData[7:0] are valid; parity is cal-
culated and checked only over these bits of the data
buses. In 16-bit mode, the full U_TxData[15:0] and
U_RxData[15:0] are valid; parity is calculated and
checked over all bits of the data buses.
• In ATM mode, the DS92UT16 can communicate with up
to 248 PHY ports using the MPhy address busses
U_TxAddr[4:0] and U_RxAddr[4:0], and the control sig-
nals U_TxCLAV[7:0], U_RxCLAV[7:0], U_TxENB[7:0]
and U_RxENB[7:0]. In PHY mode, the DS92UT16 be-
haves as a standard Level 2 device and only 31 ports are
needed using the MPhy address busses U_TxAddr[4:0]
and U_RxAddr[4:0], and the control signals
U_TxCLAV[0], U_RxCLAV[0], U_TxENB[0] and U_Rx-
ENB[0].
• All Queues from 30 to 0 of the MTB may be used. There
is one queue for each MPhy address so the use of the
queues will depend on the connected ports list defined by
the UCPL3–UCPL0 registers.
• The connected ports list defined by the UCPL3–UCPL0
registers and the connected sub-port list defined in the
UCSPL register are used. In ATM mode, these registers
are used to determine which ports should be polled. In
PHY mode, these registers are used to determine which
MPhy addresses the device should respond to during
polling.
• The sub-port address location defined by USPAL and
USPAM registers is used in ATM mode to determine the
location of the 3-bit sub-port address in the PDU cell. In
PHY mode these registers are not used.
• The CLAV mode bits CLVM[1:0] of the UCFG register
should be defined as CLVM[1:0] = 11.
The configuration of the inputs/outputs of the UTOPIA Level
2 interface for ATM Layer mode and PHY Layer mode is
shown in Figure 9.
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