DS92UT16TUF Datasheet, PDF (38/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

17.0 Microprocessor Interface Operation (Continued)
FIGURE 22. Motorola Read Cycle
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TABLE 19. Motorola Read
No.
Parameter
1 Address Setup Time before Chip Select Low
2 Chip Select Setup before Data Strobe Low
3 Read/Write Setup before Data Strobe Low
4 Data Strobe Pulse Width (Notes 6, 7)
5 Data Strobe Low to Data Low Impedance
6 Data Strobe Low to Valid Data (Notes 6, 7)
7 Data Strobe High to Data High Impedance
8 Read/Write Hold after Data Strobe High
9 Chip Select Hold after Data Strobe High
10 Address Hold after Data Strobe High
11 Data Strobe Recovery Time (Notes 6, 8)
Min
0
0
5
8 cycles
5
5
0
1 cycle
Max
Units
ns
ns
ns
10
ns
7 cycles + 15 ns
15
ns
ns
ns
ns
Note 6: “Cycle” must be greater than or equal to the cycle time of the slowest DS92UT16 clock.
Note 7: When an LVDS receiver loses or gains “lock”, the recovered clock may stay high for up to 2.5 cycles. If a processor access is in progress to one of the
registers in either of the recovered clock domains, then a READ will return the value of the last READ access, and a WRITE will not change the value of the target
register. To accommodate this possible gap in the clock, 3 cycles has been added to these timings and they should therefore be regarded as worst case. If access
time needs to be increased and a system is robust enough to accept these possible incorrect accesses then 3 cycles can be removed from these timings.
Note 8: A recovery time of 1 cycle is required between successive processor accesses.
SOFTWARE LOCK
Note that the device has a software lock mechanism imple-
mented for security. This is described in Section 6.5 CPU
INTERFACE and Section 18.1 SOFTWARE LOCK — 0x00
to 0x01 SLK0 to SLK1.
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