DS92UT16TUF Datasheet, PDF (11/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

6.0 Functional Description (Continued)
tial outputs with independent TRI-STATE^® controls for each.
The same data is transmitted over both pairs of transmit
pins. The two serial receive interfaces are completely sepa-
rate and independent and are denoted Port A and Port B.
Only one receive port is selected for traffic at any one
time. This is designated the Active Port. The Standby receive
port may be powered down. Alternatively, the Standby re-
ceive port’s OAM channel can be made available for soft-
ware communications using the ECC, and for link perfor-
mance monitoring. This allows the condition of the Standby
link to be determined. The LOCK status of both Active and
Standby ports is monitored automatically.
The transmitted data stream contains embedded clock infor-
mation. The receiver’s clock recovery circuit locks onto the
embedded clock in either a random data pattern, or by
instructing the transmitter to send SYNCH patterns. The
DS92LV16 can send SYNCH patterns on power-up or when
synchronization is lost. The latter option requires a feedback
loop in either hardware or software between the transmitter
and the receiver, but has the benefit of a faster lock time. The
LOCK status of both receive ports is reflected on external
pins and alarm/status bits that are readable via the micro-
processor port. The LOCK status, along with the currently
active port, is transmitted to the far-end receiver via the
Remote Alarm and Signalling byte of the OAM channel as
described in Section 6.3.7.1 Remote Alarm and Signaling
Byte. The recovered clocks of both receive ports are avail-
able on external pins.
A Loop Timing option is available whereby the LVDS transmit
clock can be sourced directly from the recovered clock of the
active receiver, rather than from the external transmit clock
input pin.
The transmit port and two receive ports may be indepen-
dently powered down via microprocessor control. Similarly,
the device may be forced to send SYNCH patterns on the
transmit port via microprocessor control.
To assist in designer testing and system commissioning of
the LVDS interface, the DS92UT16 has a built in BER test
facility. The device may be configured to send a PRBS
pattern in place of ATM cells. At the receiver, the device locks
onto this PRBS pattern and provides an error metric.
6.5 CPU INTERFACE
The DS92UT16 contains a flexible microprocessor port ca-
pable of interfacing to any common system processor. Via
this port, the system software can customize the behavior of
the device from the various options provided, monitor the
system performance, and activate diagnostic facilities such
as loop-backs and LVDS BER testing.
In addition to an 8-bit address and 8-bit data bus plus the
associated bus protocol control signals, the port includes an
open-drain interrupt signal. The device may assert this signal
on the detection of various alarms within the device, such as
excessive HEC errors, ECC buffer full/empty, loss of lock
etc. Any of the potential internal sources of this interrupt may
be inhibited individually via an interrupt mask.
A software lock mechanism is implemented to prevent spu-
rious modification of some of the DS92UT16 software acces-
sible registers. A predefined UNLOCK write sequence is
necessary to allow unrestricted software write access to the
DS92UT16. A corresponding LOCK write sequence will pre-
vent any software write access to the these registers. Read
access is unrestricted except as noted in the next paragraph.
See Table 9 for the LOCK and UNLOCK sequences. Only
device configuration registers such as PDU cell length, UTO-
PIA interface mode, etc. are protected in this way. All other
registers associated with the ECC, performance monitoring
and interrupts are always write accessible by the software
except as noted in next paragraph. See Section 18.1 SOFT-
WARE LOCK — 0x00 to 0x01 SLK0 to SLK1.
TABLE 9. Software Lock Sequences
Meaning
Unlock Sequence
LOCK Sequence
Sequence
1st write
2nd write
1st write
2nd write
Address
0x00
0x01
0x00
0x01
Data
0x00
0xFF
0xDE
0xAD
Powering down a Receive Port inhibits access to the asso-
ciated registers. This feature saves power when a Receive
Port is not in use. It allows re-reading the last value read
from a register associated with that Receive Port and disal-
lows writing to registers. Receive Port A (RxA) in Power-
down mode inhibits access to registers described in Section
18.21 RECEIVE PORT A LINK LABEL — 0x20 RALL to Sec-
tion 18.39 RECEIVE PORT A BIT ERROR COUNT — 0x43
to 0x45 RABEC2 to RABEC0. Receive Port B (RxB) in
Power-down mode inhibits access to registers described in
Section 18.40 RECEIVE PORT B LINK LABEL — 0x60 RBLL
to Section 18.58 RECEIVE PORT B BIT ERROR
COUNT — 0x83 to 0x85 RBBEC2 to RBBEC0. The contents
of these registers are not lost or altered in Power-down
mode.
6.6 PERFORMANCE MONITORING AND ALARMS
The DS92UT16 provides a number of performance metrics
and alarms to assist in equipment/network management.
The programmer can independently enable or disable these
alarms to raise an interrupt. See Section 14.0 Performance
Monitoring for a detailed description of the Performance
Monitoring and General Alarms.
6.7 TEST INTERFACE
The IEEE 1149.1 JTAG [4.] port on the device provides
access to the built-in test features such as boundary SCAN,
Internal SCAN and RAM BIST. It may be used to test the
device individually or as part of a more comprehensive cir-
cuit board or system test. (NOTE: The internal SCAN and
RAM BIST functions are not intended for user access.
Therefore, the device user should never assert the Test_se
pin.)
6.8 LOOPBACKS
To assist in diagnostic testing, the device provides both
LVDS interface loopbacks and ATM cell loopbacks. The
former is suitable for designer or commission testing when
the device is not passing live traffic. The latter allows cell
trace testing on live traffic. The ATM cell loopback operates
by recognizing the user-defined cell header of the special
loopback cells. The available loopback options are shown in
Table 10.
In addition to providing a live round trip test via the cell
loopbacks, the DS92UT16 helps pinpoint failures between
transmit and receive paths by counting the number of loop-
back cells received.
All loopbacks are programmable via the microprocessor
interface.
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