DS92UT16TUF Datasheet, PDF (31/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

16.0 Embedded Communication
Channel Operation (Continued)
Reset
The transmit buffer ready ETXBR bit is set indicating that the
transmit buffer ETXD7–ETXD0 can be written to and the Tx
Buffer Freeze is clear (inactive).
The transmit buffer send ETXSD bit is clear indicating that
no message is being sent and therefore EVN is clear indi-
cating to the receiver that Null data is being transmitted.
The receive buffer full ERABF bit is clear indicating that no
message has been received and therefore ESS is clear
indicating to the transmitter that it can send a message when
ready.
Assembling A Message
As the ETXBR bit is set the processor now has read/write
access to the transmit buffer ETXD7–ETXD0 and can as-
semble a message by writing to these registers in any order.
The message can be read back for checking. Writing to
these registers does not affect the ETXBR and ETXSD bits
or the EVN signal.
Transmitting A Message
To transmit a message the processor simply sets the send
bit ETXSD. This clears the ETXBR bit preventing write ac-
cess to the transmit buffer so the message being transmitted
cannot be corrupted by writes to the ETXD7–ETXD0 regis-
ters until transmission is completed. The setting of the
ETXSD bit also set the EVN signal indicating to the receiver
that Valid data is being transmitted in the F1/F2 bytes of
TC13, TC20, TC41 and TC48.
Note that transmitting a message depends on the incoming
ESS signal. If ESS is clear indicating that a message can be
sent, then the processor can write to the ETXSD bit. How-
ever, if ESS is set indicating that a message cannot be sent,
then the ETXSD bit is held in reset and cannot be written to
by the processor to initiate transmission. This provides flow
control from the receiver back to the transmitter.
Receiving A Message
As the receiver ERABF bit is clear the ESS bit is clear
indicating that the receiver can accept a message. The
receiver monitors the incoming EVN signal to determine
when valid data is being transmitted.
On detecting EVN set the receiver uses the TC number to
extract the 8 ECC message bytes from the incoming data
stream. If an errored HEC is detected on any of the ECC
message bytes then the receiver assumes all 8 bytes are
corrupted and will re-extract the entire message on the next
frame. The transmitter will continue to transmit the message
as long as the ESS signal is clear.
When the receiver determines that it has received the entire
message it sets the receive buffer full ERABF bit. This
prevents the receive buffer ERAD7–ERAD0 being updated
by the incoming ECC bytes so that the message cannot be
overwritten. It also raises an interrupt to the local processor
to indicate that a valid ECC message has been received.
The setting of the ERABF bit also sets the ESS signal back
to the transmitter indicating that it should stop transmission.
This clears the ETXSD bit which clears the EVN signal thus
indicating that transmitted ECC data is Null (not valid).
At this stage the receive buffer is full and cannot receive any
further messages. The transmit buffer ready ETXBR is still
clear meaning that no new messages can be assembled and
ETXSD is held clear so no new messages can be transmit-
ted. This flow control ensures that no new messages will be
transmitted until the current received message is read. This
situation will remain until the received message is read by
the local processor.
Reading A Message
The setting of the ERABF bit in the receiver raises an
interrupt to the local processor indicating that a valid ECC
message has been received and can be read. The receive
buffer registers ERAD7–ERAD0 are read only. The proces-
sor may read theses registers in any order and the reading of
them has no affect on the ERABF bit or the ESS signal.
When the processor is finished reading the message from
the buffer it writes to the ERABF bit to clear it. This allows the
receiver to receive a new message. The clearing of the
ERABF bit clears the ESS signals indicating to the transmit-
ter that it can send another message.
Transmitting a New Message
The clearing of the incoming ESS signal causes the trans-
mitter to set the transmit buffer ETXBR bit. This allows write
access to the transmit buffer ETXD7–ETXD0 for the assem-
bly of a new message. It also releases the ETXSD bit from
reset and the processor can now set this bit to send a new
message.
At this transmitter stage, the ETXBR bit is set, the ETXSD bit
is clear, and EVN is clear. At the receiver, the ERABF bit is
clear and the ESS signal is clear. This is the same situation
as after reset and therefore, the same sequence as above
can be followed to transmit a new message.
Note that the transmit buffer registers can be modified or
overwritten to assemble a new message for transmission, or
the existing message can be resent simply by setting the
ETXSD bit again.
SUMMARY
• Tx - If the ETXBR bit is set, then write the message to the
ETXD7–ETXD0 registers.
• Tx - Set the ETXSD bit to send the message. This clears
ETXBR.
• Rx - When full message is received, the ERABF bit is set
and this raises an interrupt.
• Rx - After reading the message, clear the ERABF bit to
allow new message to be received.
• Tx - The clearing of the ERABF bit sets the ETXBR bit,
which allows a new message to be assembled and trans-
mitted.
Flow Charts
The Flow Charts in Figures 16, 17 summarize the control of
the ECC receive and transmit.
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