DS92UT16TUF Datasheet, PDF (34/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

16.0 Embedded Communication Channel Operation (Continued)
FIGURE 18. ECC Signalling with Active and Standby Links
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17.0 Microprocessor Interface
Operation
The DS92UT16 contains a flexible microprocessor port ca-
pable of interfacing to either Intel or Motorola processors. In
addition to an 8-bit address and 8-bit data bus plus the
associated bus protocol control signals, the port includes an
open-drain interrupt signal. This signal may be asserted on
the detection of various alarms within the device and any of
the potential internal sources of this interrupt may be indi-
vidually inhibited via an interrupt mask.
Powering down a Receive Port inhibits access to the asso-
ciated registers. This feature saves power when a Receive
Port is not in use. It allows re-reading the last value read
from a register associated with that Receive Port and disal-
lows writing to that port’s registers. Receive Port A (RxA) in
Power-down mode inhibits access to registers described
inSection 18.21 RECEIVE PORT A LINK LABEL — 0x20
RALL to Section 18.39 RECEIVE PORT A BIT ERROR
COUNT — 0x43 to 0x45 RABEC2 to RABEC0. Receive Port
B (RxB) in Power-down mode inhibits access to registers
described in Section 18.40 RECEIVE PORT B LINK
LABEL — 0x60 RBLL to Section 18.58 RECEIVE PORT B
BIT ERROR COUNT — 0x83 to 0x85 RBBEC2 to RBBEC0.
The contents of these registers are not lost or altered in
Power-down mode.
Typical processor Read and Write cycles for this device are
shown in Figures 19, 20, 21, 22. The associated timing for
each cycle is given in Tables 16, 17, 18, 19.
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