DS92UT16TUF Datasheet, PDF (45/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
18.4 LVDS CONTROL — 0x04 LVC
7
Reserved
6
Reserved
5
TXPWDN
TABLE 24. LVC
4
TXBDEN
3
TXADEN
2
TXSYNC
1
RAPWDN
0
RBPWDN
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x3B
The LVDS control register configures the LVDS serializer/deserializers.
• TXPWDN Transmit section LVDS power down. Set = Power Up and Clear = Power Down. This register value is combined with
the LVDS_TxPwdn pin to generate the internal power down setting for transmit section. If either this register bit or the
LVDS_TxPwdn pin is clear then the transmit LVDS section is powered down.
• TBDEN LVDS B Transmit data output enable. Set = Enable and Clear = Disable. This register value is combined with the
LVDS_BDenb pin to generate the output enable for the LVDS transmit section B. If either this register bit or the LVDS_BDenb
pin is clear then the transmitter B output is disabled.
• TXADEN LVDS A Transmit data output enable. Set = Enable and Clear = Disable. This register value is combined with the
LVDS_ADenb pin to generate the output enable for the LVDS transmit section A. If either this register bit or the LVDS_ADenb
pin is clear then the transmitter A output is disabled.
• TXSYNC Transmit LVDS synchronization pattern. Set = Enable and Clear = Disable. This register value is combined with the
LVDS_Synch pin to generate the SYNCH input to the LVDS transmit section. If either this register bit or the LVDS_Synch pin
is set then SYNCH patterns are output from the LVDS transmit section.
• RAPWDN Receive Port A LVDS power down. Set = Power Up and Clear = Power Down. This register value is combined with
the LVDS_APwdn pin to generate the internal power down setting for receive Port A. If either this register bit or the
LVDS_APwdn pin is clear then the receive Port A LVDS section is powered down.
• RBPWDN Receive Port B LVDS power down. Set = Power Up and Clear = Power Down. This register value is combined with
the LVDS_BPwdn pin to generate the internal power down setting for receive Port B. If either this register bit or the
LVDS_BPwdn pin is clear then the receive Port B LVDS section is powered down.
18.5 PDU CONFIGURATION — 0x05 PDUCFG
7
Reserved
6
UP[2]
5
UP[1]
TABLE 25. PDUCFG
4
UP[0]
3
UDF
2
UA[2]
1
UA[1]
0
UA[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The PDU Configuration register defines the contents and size of the PDU cells. The register does this by defining the size of the
User Prepend, whether or not the UDF is to be transported, and the size of the User Append. The total size of the PDU must be
in the range 52 to 64 bytes. Therefore the total size of the User Prepend, plus UDF and User Append must not exceed 12 bytes.
Further, as the DS92UT16 operates with an internal 16 bit data path the size of the User Prepend and User Append is defined
in words (16 bits/2 bytes). If the UDF is to be transported, then in UTOPIA 16-bit mode UDF1 and UDF2 bytes are transported
and in UTOPIA 8-bit mode the UDF byte is transported.
• UP[2:0] The UP bits define the length of the User Prepend. Range 0 to 6 words.
• UDF The UDF bit when set indicates that the UDF word should be transported. When cleared the UDF word is not transported.
• UA[2:0] The UA bits define the length of the User Append. Range 0 to 6 words.
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