DS92UT16TUF Datasheet, PDF (73/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

20.0 Package (Continued)
Ball
B8
C8
D8
C9
C11
C12
G9
B5
B6
C5
C6
A8
B9
D9
D12
E12
A5
D5
D6
L2
D13
F11
F10
F13
G11
G12
H11
G13
H12
F14
H13
H14
J13
J14
N13
N14
P14
L11
P13
M12
P12
K10
N12
P11
N11
M11
M10
J10
Pin Name
PGND
PGND
PGND
PGNDA
PGNDA
PGNDA
PGNDA
PGNDB
PGNDB
PGNDB
PGNDB
PV_DD
PV_DD
PV_DDA
PV_DDA
PV_DDA
PV_DDB
PV_DDB
PV_DDB
Reset_n
Test_se
U_RxAddr[0]
U_RxAddr[1]
U_RxAddr[2]
U_RxAddr[3]
U_RxAddr[4]
U_RxCLAV [0]
U_RxCLAV [1]
U_RxCLAV [2]
U_RxCLAV [3]
U_RxCLAV [4]
U_RxCLAV [5]
U_RxCLAV [6]
U_RxCLAV [7]
U_RxData [0]
U_RxData [1]
U_RxData [2]
U_RxData [3]
U_RxData [4]
U_RxData [5]
U_RxData [6]
U_RxData [7]
U_RxData [8]
U_RxData [9]
U_RxData [10]
U_R xData [11]
U_RxData [12]
U_RxData [13]
TABLE 96. Pin Locations — BGA196 Package (Continued)
Signal Type
Description
GND
GND for Transmit PLL
GND
GND for Transmit PLL
GND
GND for Transmit PLL
GND
GND for PLL A
GND
GND for PLL A
GND
GND for PLL A
GND
GND for PLL A
GND
GND for PLL B
GND
GND for PLL B
GND
GND for PLL B
GND
GND for PLL B
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Input LVTTL
Transmit PLL V_DD
Transmit PLL V_DD
V_DD for PLL A
V_DD for PLL A
V_DD for PLL A
V_DD for PLL B
V_DD for PLL B
V_DD for PLL B
Chip Reset Control
Input LVTTL
Scan Enable
BiDir LVTTL
Address of MPHY Device Being Polled or Selected
BiDir LVTTL
Address of MPHY Device Being Polled or Selected
BiDir LVTTL
Address of MPHY Device Being Polled or Selected
BiDir LVTTL
Address of MPHY Device Being Polled or Selected
BiDir LVTTL
Address of MPHY Device Being Polled or Selected
BiDir LVTTL
Receive Cell Available — Normal/Extended PHY Port Control
Input LVTTL
Receive Cell Available — Normal/Extended PHY Port Control
Input LVTTL
Receive Cell Available — Normal/Extended PHY Port Control
Input LVTTL
Receive Cell Available — Normal/Extended PHY Port Control
Input LVTTL
Receive Cell Available — Extended PHY Port Control
Input LVTTL
Receive Cell Available — Extended PHY Port Control
Input LVTTL
Receive Cell Available — Extended PHY Port Control
Input LVTTL
Receive Cell Available — Extended PHY Port Control
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
BiDir LVTTL
Receive Data Bus, from the PHY Layer Device(s)
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