DS92UT16TUF Datasheet, PDF (19/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

9.0 MTB Queue Configuration
(Continued)
It is further recommended that any queue that is not being
used is set with a threshold of zero. When a queue has
reached its programmed threshold the device flow control
mechanism will prevent the far end device from accepting
cells for that MPHY address. Therefore, by setting the
threshold of an unused queue to zero, it prevents the UTO-
PIA interface of the far end device from accepting cells for
that MPHY address by either, not asserting the CLAV for that
MPHY address when in PHY Mode, or not selecting that
MPHY address when in ATM mode.
Also, note that setting a threshold of zero will cause the
corresponding Queue Full bit in the MTBQFL3–MTBQFL0
registers to be continuously set for that queue.
TABLE 12. Recommended Maximum MTB Queue Thresholds
Number of
Queues in Use
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Recommended
Threshold
4
4
5
5
5
6
6
7
7
8
9
10
10
11
12
4
Number of
Queues in Use
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Recommended
Threshold
15
16
18
20
23
26
29
34
39
47
58
74
100
100
154
9.2 MULTIPLE BRIDGE MTB CONFIGURATION
When UTOPIA-LVDS bridges are used in parallel as in Fig-
ure 5 the PHY mode DS92UT16s will forward all cells on the
UTOPIA TxData bus across the LVDS bridge. Cells that are
not addressed for PHYs on a bridge will accumulate in the
MTBs of the ATM mode DS92UT16s. If too many cells
accumulate the MTB will become full and traffic will be
stopped over that bridge. To prevent filling the MTBs PHY
port addresses must be distributed evenly across all bridges
in the system. Additionally, the MTB queue threshold of any
ports not in the Connected Ports List should be set to 0 in
order to limit the number of cells that can accumulate.
Table 13 lists the minimum number of ports that must be
assigned to each bridge for the total number of ports in the
system.
TABLE 13. Minimum Ports per Bridge in a Mult-Bridge
System
Total Ports Used
31
30
29
28
27
26
25
24
Minimum Number
of Ports per Bridge
10
9
8
7
6
5
4
3
23
2
22
1
10.0 Configuration and Traffic
Inhibit Operation
Modifying some device configuration settings should not be
carried out while traffic is flowing. A mechanism to inhibit
traffic is provided, which should be used when changing any
of the settings contained in the PDUCFG, UCFG, USPAL or
USPAM registers.
The Traffic Inhibit mechanism causes traffic to stop. The
UTOPIA interface will stop transmitting and receiving cells,
the LVDS transmit section will transmit Idle cells, and the
incoming cells on the active LVDS receive port will be dis-
carded. It is controlled by the Configuration Traffic Inhibit
(CTI) and Traffic Inhibit Status (TIS) bits of the General
Control and Status (GCS) register, see Section 18.3 GEN-
ERAL CONTROL AND STATUS — 0x03 GCS.
The processor should set the CTI bit before changing any of
the PDUCFG, UCFG, USPAL or USPAM register settings.
This will initiate the Traffic Inhibit mechanism. The TIS bit
should then be polled. When the TIS bit is set, then traffic is
inhibited.
The MTB and FIB queues MUST be flushed at this stage.
Use the FIBFL and MTBFL bits of the QFL register described
in Section 18.69 QUEUE FLUSH — 0xD8 QFL to accomplish
the queue flushing. Set these bits to flush the queues and
then poll these bits to determine when flushed. The queue
flushing is complete when these bits are clear.
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