DS92UT16TUF Datasheet, PDF (6/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

6.0 Functional Description (Continued)
20031604
Note: Default MTB queue thresholds must be changed to use this configuration. See Section 9.2 MULTIPLE BRIDGE MTB CONFIGURATION
FIGURE 5. Multi-Bridge System Example
Parity generation and checking is available in all modes.
To support systems where routing tags and/or padding are
added to the ATM cells at a previous device, the UTOPIA
interface on DS92UT16 may be programmed to handle non-
standard ATM cells of length 52 bytes up to 64 bytes. See
Figure 6. In all cases, the Start Of Cell (SOC) signal must
correspond to the first byte or word of the extended cell.
Back-to-back cell transfer is supported in all modes.
When configured as an ATM layer device, receive polling
and transmit polling of those Ports with queued cells is
Round-Robin. The DS92UT16 will only poll those PHY ports
configured as active.
6.2 TRAFFIC BUFFERS
6.2.1 Down-Bridge FIFO
In the down-bridge direction, a simple 3 cell FIFO (with 30
cell overhead) is used to rate adapt the data from the UTO-
PIA clock domain to the LVDS clock domain for transmis-
sion. Per port queuing and back pressure/flow control is
handled by the corresponding up-bridge Multi-port Traffic
Buffer in the far end DS92UT16 device as described in
Section 6.2.2 Up-Bridge Multi-Port Traffic Buffer and Section
6.3.5 Flow Control.
6.2.2 Up-Bridge Multi-Port Traffic Buffer
In the up-bridge direction, a 160 cell linked list buffer is
shared across up to 31 port queues. This is called the
Multi-port Traffic Buffer. Although each MPHY may be con-
nected to 8 sub-ports/PHY’s, the MTB has a single queue
per MPHY port, as it only uses the 5-bit MPHY address and
does not access the sub-port address bits.
Each port has a programmable upper fill threshold. In the
up-bridge direction, queue overflow is avoided through the
means of a per queue flow control protocol embedded in the
LVDS link as described in Section 6.3.5 Flow Control.
Should any queue reach this upper threshold, back-pressure
is applied via the flow control mechanism over the serial link
to the down-bridge (transmitting) device which uses the
normal UTOPIA flow control handshaking to prevent any
more cells being transferred and thus prevent overflow.
The individual queue per port architecture ensures that the
flow control is non-blocking across the 31 ports. However,
the 8 sub-ports within each port can be blocking.
Furthermore, as is the nature of link-list buffers, each queue
may be over-assigned memory space, working on the as-
sumption that not every queue will back up simultaneously.
To accommodate the rare occasions where the buffer as a
whole approaches full but individual queues are below their
full threshold, the device also compares the overall buffer fill
against a threshold. The flow control mechanism provides a
global ‘halt’ command to ensure that no cells will be lost if the
overall buffer should approach the overflow condition.
6.3 TRANSMISSION CONVERGENCE SUB-LAYER
(TCS)
In the down-bridge direction, the Transmission Convergence
Sub-layer (TCS) Assembler performs cell rate de-coupling.
The TCS Assembler then prepares the cells for transport
over the LVDS link by packaging them within link Transport
Containers (TC).
In the up-bridge direction, the TCS Disassemblers unpack
the link transport containers and route the cells to the Multi-
port Traffic Buffer.
MPHY address, flow control, and OAM information is em-
bedded within the link transport containers.
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