DS92UT16TUF Datasheet, PDF(10/86 Page) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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DS92UT16TUF Datasheet, PDF (10/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

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6.0 Functional Description (Continued)

Buffer with a corresponding Rx Buffer Full Flag. All bytes of

the buffers are software read/write accessible. Tx Buffer

Ready is read only.

At the ECC transmit side, the reset state sets the Tx Buffer

Ready flag and clears the Tx Buffer Send flag. Then the

software assembles a message for transmission in the Tx

Buffer. To send a message, the software simply sets Tx

Buffer Send, which automatically clears Tx Buffer

Ready. The contents of the Tx Buffer are transmitted to the

far-end. The Tx Buffer will automatically be retransmitted

until the far-end indicates that it has been successfully re-

ceived. When notified by the far end of successful reception,

Tx Buffer Ready is set and an interrupt raised to the software

to indicate successful transmission. A new message may

now be assembled in the Tx Buffer and transmitted by

setting Tx Buffer Send. As all the Tx Buffer bytes are read/

write, the message to be transmitted can be assembled in

any order and read back by the software before transmis-

sion. The same message can be retransmitted simply by

setting Tx Buffer Send again.

At the ECC receive side, the reset state clears the Rx Buffer

Full flag. When all 8 bytes of a message have been success-

fully received and stored in the Rx Buffer, the Rx Buffer Full

flag is set and an interrupt raised. As all the Rx Buffer bytes

are read/write, the message can be read in any order by the

software. A new message will not overwrite the current re-

ceived message until the Rx Buffer Full flag is cleared by the

software indicating that the current Rx Buffer has been read

and a new message can be received.

The ECC data flow is controlled across the link using the

EVN, ESSA, and ESSB bits of the Remote Alarm and Sig-

naling byte (Section 6.3.7.1 Remote Alarm and Signaling

Byte).

As there are two independent LVDS receive ports, the

DS92UT16 has two independent ECC receive sections.

These are assigned to the LVDS receive ports Port A and

Port B. The ECC of the standby link may therefore be used

for software communication.

Section 16.0 Embedded Communication Channel Operation

describes the operation and control of the ECC in detail.

6.3.7.4 BIP16

A Bit-Interleaved-Parity mechanism provides a live error per-

formance metric on the LVDS link. A BIP16 value is calcu-

lated over a previous block of 28 containers and inserted in

the F1/F2 bytes of containers 27 and 55, as shown in Sec-

tion 6.3.6 F Channel Byte Usage Within the Frame. At the far

end, the re-calculated BIP16 values are compared against

the received values. Any bit errors in this comparison are

counted. Should the number of errors exceed a programmed

threshold, then an interrupt may be raised.

6.3.7.5 F Channel (Flow Control and OAM) Bandwidth

Analysis

This section analyses the bandwidth used by the various

components of the F Channel. The figures are dependent

upon the link bandwidth and the size of the PDU/ATM cells

being carried in the Transport Containers. This illustration is

restricted to 800 Mbps and PDU sizes of 52 and 64 bytes. By

adding the 4 bytes for the F Channel, the TCs are then 56

and 68 bytes respectively.

Table 6 illustrates the number of bytes used for each function

in the F Channel. The top row gives the total number of

Transport Containers per Frame as 56. It then shows the

number of bytes in each Frame for OAM and Flow Control.

There is a total of 112 bytes in each Frame for the F

Channel.

Table 7 shows the bit rate used by each portion of the F

Channel. The larger 68 byte container uses a lower propor-

tion of the channel bandwidth for F Channel functions.

Table 8 shows the percentage of the channel bandwidth

used for each of the functions. The total F Channel band-

width is only 3.57% of total bandwidth even with the smaller

container size.

TABLE 6. F Channel Bandwidth â Bytes

Number of Transport Containers in Frame

(8 rows x 7 columns)

Bytes per Frame for Remote Alarms and

Signalling

Bytes per Frame for Link Label

Bytes per Frame for ECC

Bytes per Frame Reserved

Bytes per Frame for BIP16

Bytes per Frame for OAM

Bytes per Frame for Flow Control

Bytes per Frame for F Channel

112

TABLE 7. F Channel Bandwidth â Mbps

Link BW - Mbps

Container Size - Bytes

Remote Alarm BW - Mbps

Link Label BW - Mbps

ECC BW - Mbps

Reserved BW - Mbps

BIP16 BW - Mbps

OAM BW - Mbps

Flow Control BW - Mbps

F Channel BW - Mbps

800

0.26

2.04

0.51

1.02

4.08

24.49

28.57

800

0.21

1.68

0.42

0.84

3.36

20.17

23.53

TABLE 8. F Channel Bandwidth â Percentage

Link BW - Mbps

Container Size - Bytes

Remote Alarm BW%

Link Label BW%

ECC BW%

Reserved BW%

BIP16 BW%

OAM BW%

Flow Control BW%

F Channel BW%

800

0.03

0.26

0.21

0.06

0.05

0.13

0.10

0.51

0.42

3.06

2.52

3.57

2.94

6.4 LVDS PHYSICAL INTERFACE

The DS92UT16 provides one dual transmit and two indepen-

dent receive high speed LVDS serial interfaces with 800

Mbps bandwidth. The LVDS Interface transmits and receives

data over lightly loaded backplanes or up to 10m of

cable. The single transmit block drives two pairs of differen-

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