DS92UT16TUF Datasheet, PDF (22/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

11.0 Cell/Frame Delineation and
Descrambler Operation (Continued)
lock, then the transmitted RDSLL = 1. At the far end device,
this is stored as RARDSLL or RBRDSLL, depending on
which port it is connected to. When this bit is set for the
active receive port, it causes the TCS Assembler to transmit
the Scrambler sequence embedded in Idle cells. The De-
scrambler loads this sequence and attempts to lock to it.
Once the Descrambler locks to this sequence, it clears the
RDSLL bit transmitted to the far-end device, which causes
the far-end device to stop sending the Scrambler sequence
embedded in Idle cells and to begin sending real traffic cells.
The Descrambler synchronization state diagram is shown in
Figure 14.
FIGURE 14. State Diagram for Descrambler Synchronization
20031613
D_HUNT — On reset, the Descrambler synchronization state
machine starts in the D_HUNT state and the Descrambler is
not in Lock. When TC delineation has been achieved, the
transmitted Scrambler sequence from the far-end device is
loaded into the Descrambler. The state machine enters the
D_PRESYNC state.
D_PRESYNC — The received scrambler sequences and
predicted sequences are compared for each TC. For each
correct prediction, a confidence counter increments, and for
each incorrect prediction, the confidence counter is decre-
mented. When the confidence counter reaches RHO, then
the state machine moves to the D_SYNCH state and the
system is said to have achieved scrambler Lock. If the
confidence counter reaches zero then the state machine
moves back to the HUNT state.
D_SYNC — The comparison of received scrambler se-
quences and predicted sequences is repeated for each
Frame. For each correct prediction, a confidence counter is
decremented, and for each incorrect prediction, the confi-
dence counter is incremented. The confidence counter has a
lower limit of zero. If the confidence counter reaches PSI,
then the state machine moves back to the D_HUNT state
and the Descrambler is out of Lock.
The state machine will also return directly to D_HUNT if TC
delineation is lost.
The values of PSI and RHO are programmable indepen-
dently for Port A and Port B. They are contained in the
RADSLKT and RBDSLKT registers (Section 18.38 RE-
CEIVE PORT A DESCRAMBLER LOCK
THRESHOLDS — 0x42 RADSLKT and Section 18.57 RE-
CEIVE PORT B DESCRAMBLER LOCK
THRESHOLDS — 0x82 RBDSLKT). On reset PSI = 8 and
RHO = 8.
11.4 ANALYZING LOCK AND SYNCHRONIZATION TIME
After the DS92UT16 LVDS receiver’s PLL locks onto the
incoming serial data stream and begins to recover data, it
must achieve TC lock, then frame lock and descrambler lock
before transferring cells. The number of cycles to complete
this synchronization depends on the PDU length as well as
the byte location in the TC and frame where the receiver
begins synchronizing.
Here are the assumptions for this example on calculating the
synchronization time.
• PDU length = 64 bytes (maximum possible) = 32 cycles
(16 bit data path)
• Max TC length =PDU + 4 bytes = 34 cycles
• Frame = 56 TC = 1904 cycles
Once the LVDS Receive input PLL locks to the incoming
serial data stream and recovers data bits, the DS92UT16
searches for a TC HEC byte. Assuming that the DS92UT16
just missed a HEC when the LVDS PHY locked, it will take a
minimum of one TC to find the HEC byte. Next, the
DS92UT16 will continue finding correct TC HECs until it
matches the number in the confidence counter (default set-
ting is DELTA = 8). The TC delineation is now in sync.
Next, the UT16 will start looking for SOF HECs that indicate
a start-of-frame. Assuming a SOF has just passed, the max
time to find an SOF should be 1 Frame. Now the UT16 will
collect frames until the correct number matches the confi-
dence counter (default setting is SIGMA = 8). When the
correct number of SOFs matches the confidence counter,
the frame delineation is in sync.
Simultaneous with the frame delineation, the DS92UT16 will
synchronize and lock the descrambler. The lock procedure
begins with the transmitting DS92UT16 sending the scram-
bler sequence in idle cells. It does this automatically on reset
www.national.com
22