DS92UT16TUF Datasheet, PDF (50/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
ERRBIP1 0x17
ERRBIP0 0x18
7
EBIP1[7]
EBIP0[7]
6
EBIP1[6]
EBIP0[6]
TABLE 36. ERRBIP1–ERRBIP0
5
EBIP1[5]
EBIP0[5]
4
EBIP1[4]
EBIP0[4]
3
EBIP1[3]
EBIP0[3]
2
EBIP1[2]
EBIP0[2]
1
EBIP1[1]
EBIP0[1]
0
EBIP1[0]
EBIP0[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The Error BIP Mask registers controls how errors are introduced into the BIP bytes when bit ERBIP of the TERRCTL register is
set. If a bit is set in the ERRBIP1 or ERRBIP0 register then the corresponding bit in the transmitted BIP is inverted. ERRBIP1
corresponds to the first transmitted BIP byte and ERRBIP0 corresponds to the second transmitted BIP byte.
18.17 ERROR HEC MASK — 0x19 ERRHEC
7
EHEC[7]
6
EHEC[6]
5
EHEC[5]
TABLE 37. ERRHEC
4
EHEC[4]
3
EHEC[3]
2
EHEC[2]
1
EHEC[1]
0
EHEC[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The Error HEC Mask register controls the introduction of errors into the HEC byte when the ERFHEC and/or ERCHEC bits of the
TERRCTL register are set. If a bit is set in the ERRHEC register, then the corresponding bit in the transmitted HEC is inverted.
18.18 ATM AND LVDS LOOPBACK CONTROL — 0x1A ALBC
7
Reserved
6
LNEN
5
LNSEL
TABLE 38. ALBC
4
LCLA
3
LCLB
2
TXLVLB
1
D2ULB
0
D2DLB
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
The ATM and LVDS Loopback Control register controls the loopback functions of the device.
Note that the LVDS Line and Local Loopbacks should not be on at the same time.
• LNEN LVDS Line Loopback enable. Set = ON and Clear = OFF. When set this enables the loopback of the LVDS receive
section, determined by LNSEL, to the transmitter.
• LNSEL LVDS Line Loopback receive section select. Set = Receive B and Clear = Receive A.
• LCLA LVDS Local Loopback transmit to receive Port A. Set = ON and Clear = OFF.
• LCLB LVDS Local Loopback transmit to receive Port B. Set = ON and Clear = OFF.
• TXLVLB When set, this initiates the transmission of a single loopback cell Down Bridge on the LVDS transmitter. This cell will
be transmitted with the MPhy address defined in the ALBMP register and will have a header format as defined in the
ALBCF3–ALBCF0 registers. When the bit is clear, the cell has been transmitted. The processor sets the bit to initiate the
transmission and then polls this bit to determine when transmission has been completed, at which time the process can be
repeated to transmit another loopback cell. See Section 15.1 ATM CELL LOOPBACK.
• D2ULB When set, this enables the ATM Down2Up loopback circuit. Any incoming cells from the UTOPIA interface which
match the format of ALBCF3–ALBCF0, masked by the ALFLT3–ALFLT0 registers, are not stored in the FIB traffic queue but
transmitted back out over the UTOPIA interface. See Section 15.1 ATM CELL LOOPBACK.
• U2DLB When set, this enables the ATM Up2Down loopback circuit. Any incoming cells from the active LVDS receive port
which match the format of ALBCF3–ALBCF0 registers, masked by the ALFLT3–ALFLT0 registers, are not stored in the MTB
traffic queue but transmitted back out over the LVDS transmitter. Note that although there are two independent receivers, this
loopback is designed to operate on live traffic and so only affects cells from the active receiver as defined by the LBA bit of
the LKSC register. See Section 15.1 ATM CELL LOOPBACK.
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