DS92UT16TUF Datasheet, PDF (60/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
18.47 RECEIVE PORT B HEC THRESHOLD — 0x71 to 0x73 RBHECT2 to RBHECT0
RBHECT2
0x71
RBHECT1
0x72
RBHECT0
0x73
7
RBHECT2[7]
6
RBHECT2[6]
TABLE 67. RBHECT2–RBHECT0
5
RBHECT2[5]
4
RBHECT2[4]
3
RBHECT2[3]
2
RBHECT2[2]
RBHECT1[7] RBHECT1[6] RBHECT1[5] RBHECT1[4] RBHECT1[3] RBHECT1[2]
RBHECT0[7] RBHECT0[6] RBHECT0[5] RBHECT0[4] RBHECT0[3] RBHECT0[2]
1
RBHECT2[1]
RBHECT1[1]
RBHECT0[1]
0
RBHECT2[0]
RBHECT1[0]
RBHECT0[0]
Type:
Read/Write
Software Lock: No
Reset Value: 0xFF
The RBHECT2, RBHECT1 and RBHECT0 registers contain the Port B received erred HEC threshold. When the error count
RBHECC equals the threshold RBHECT, then the RBXHEC alarm will be set.
These registers should not be set to all zeroes.
• RBHECT2–RBHECT0 Most significant byte RBHECT2 and least significant byte RBHECT0.
18.48 RECEIVE PORT B BIP COUNT — 0x74 to 0x76 RBBIPC2 to RBBIPC0
TABLE 68. RBBIPC2–RBBIPC0
RBBIPC2 0x74
RBBIPC1 0x75
RBBIPC0 0x76
7
RBBIPC2[7]
RBBIPC1[7]
RBBIPC0[7]
6
RBBIPC2[6]
RBBIPC1[6]
RBBIPC0[6]
5
RBBIPC2[5]
RBBIPC1[5]
RBBIPC0[5]
4
RBBIPC2[4]
RBBIPC1[4]
RBBIPC0[4]
3
RBBIPC2[3]
RBBIPC1[3]
RBBIPC0[3]
2
RBBIPC2[2]
RBBIPC1[2]
RBBIPC0[2]
1
RBBIPC2[1]
RBBIPC1[1]
RBBIPC0[1]
0
RBBIPC2[0]
RBBIPC1[0]
RBBIPC0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The RBBIPC2, RBBIPC1 and RBBIPC0 registers contain the Port B received errored BIP count.
• RBBIPC2–RBBIPC0 This register must be read in the order of most significant byte RBBIPC2first and least significant byte
RBBIPC0 or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to 0x000000 but will stick at
0xFFFFFF.
18.49 RECEIVE PORT B BIP THRESHOLD — 0x77 to 0x79 RBBIPT2 to RBBIPT0
RBBIPT2 0x77
RBBIPT1 0x78
RBBIPT0 0x79
7
RBBIPT2[7]
RBBIPT1[7]
RBBIPT0[7]
6
RBBIPT2[6]
RBBIPT1[6]
RBBIPT0[6]
TABLE 69. RBBIPT2–RBBIPT0
5
RBBIPT2[5]
RBBIPT1[5]
RBBIPT0[5]
4
RBBIPT2[4]
RBBIPT1[4]
RBBIPT0[4]
3
RBBIPT2[3]
RBBIPT1[3]
RBBIPT0[3]
2
RBBIPT2[2]
RBBIPT1[2]
RBBIPT0[2]
1
RBBIPT2[1]
RBBIPT1[1]
RBBIPT0[1]
0
RBBIPT2[0]
RBBIPT1[0]
RBBIPT0[0]
Type:
Read/Write
Software Lock: No
Reset Value: 0xFF
The RBBIPT2, RBBIPT1 and RBBIPT0 registers contain the Port B received erred BIP threshold. When the error count RBBIPC
equals the threshold RBBIPT, then the RBXBIP alarm will be set.
These registers should not be set to all zeroes.
• RBBIPT2–RBBIPT0 Most significant byte RBBIPT2 and least significant byte RBBIPT0.
18.50 RECEIVE PORT B PERFORMANCE ALARMS — 0x7A RBPA
7
Reserved
6
Reserved
5
Reserved
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
TABLE 70. RBPA
4
Reserved
3
Reserved
2
Reserved
1
RBXHEC
0
RBXBIP
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